Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

Abstract: A compound semiconductor laminate substrate comprising two single-crystalline compound semiconductor substrates directly bonded together and laminated, the single-crystalline compound semiconductor substrates having the same composition including A and B as constituent elements and having the same atomic arrangement, characterized in that the front and back surfaces of the laminate substrate are polar faces comprising the same kind of atoms of A or B, and that a laminate interface comprises a bond of atoms of either B or A and is a unipolar anti-phase region boundary plane in which the crystal lattices of the atoms are matched. In this way, the polar faces of the front and rear surfaces of the compound semiconductor laminate substrate are made monopolar, thereby facilitating semiconductor element process designing, and making it possible to manufacture a low-cost, high-performance, and stable semiconductor element without implementing complex substrate processing.

Abstract: The present invention provides a display panel including a base substrate, a plurality of pixel units, and a power signal structure. A display area of the display panel includes a lower display area, a middle display area, and an upper display area. The power signal structure includes a VDD power cable, a plurality of VDD signal lines, and a VDD lead-in portion. The VDD lead-in portion is electrically connected to each of the VDD signal lines through holes provided in an insulated layer in the middle display area. Therefore, the VDD power signals provided by a driving chip are introduced from the middle display area, and then transmitted from the middle display area to each of the pixel units by the VDD signal lines, which can effectively reduce the VDD voltage drop in an organic light emitting diode (OLED) panel, thereby significantly improving brightness uniformity of the OLED panel.

Abstract: A display device may include a substrate, an organic light emitting layer overlapping the substrate and including an opening, and a holed insulating layer positioned between the substrate and the organic light emitting layer. The holed insulating layer may include a first through hole, a first groove, and a first undercut. A position of the opening may overlap a position of the first groove. The first groove may surround the first through hole in a plan view of the display device. The first undercut may surround the first groove in the plan view of the display device.

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

Abstract: A light-emitting device includes a substrate having a top surface, wherein the top surface includes a first portion and a second portion; a first semiconductor stack on the first portion, including a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, including a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack includes a dislocation stop layer; and wherein the first side wall and the second portion of the top surface form an acute angle ? between thereof.

Abstract: A display device may include a substrate, pixels, and a crack mitigation structure. The substrate may include a main region, a sub-region, and a bending region. The bending region may be connected between the main region and the sub-region and may include a curved outline section. The pixels may be disposed on the main region. The crack mitigation structure may be disposed on the bending region. A section of the crack mitigation structure may be substantially parallel to the curved outline section.

Abstract: A light emitting device includes: a lightguide plate including a first surface on which a plurality of first recesses are provided; a light-reflective resin layer located on a bottom portion of each first recess; a plurality of light emitting elements each having an upper surface and a lateral surface, wherein each one of the plurality of light emitting elements is arranged in a corresponding one of the plurality of first recesses; and a plurality of wavelength conversion members, wherein: the upper surface of each light emitting element is attached to the light-reflective resin layer; and each of the plurality of wavelength conversion members covers the lateral surface of the light emitting element in the first recess.

Abstract: A crane includes a boom adapted for lifting a load and a sensor adapted for measuring the side deflection or twist of the boom during the lifting of the load. The crane may also include a system for detecting side deflection in the boom using a first sensor mounted to the boom for sensing a first value corresponding to deflection of the boom, a second sensor for sensing a second, reference value, and a controller for comparing the first and second values to determine a deflection amount. An operator may be notified if the side deflection or twist values exceed a predetermined value. Side deflection or twist values for the boom during a lifting operation may also be logged by a data recording device for later use.

Abstract: An organic light emitting diode (OLED) display panel and a method of manufacturing thereof. The display panel including: a baseplate comprising a color film layer; a first transparent conductive layer including a first region corresponding to the color film layer and a second region corresponding to a region for forming a gate lamination layer; an active region including a first active region and a second active region, the first active region is disposed above the first region, and the second active region is disposed above the second region; a gate lamination layer, an interlayer dielectric layer, a second transparent conductive layer, a planarization layer, an anode and a pixel defining layer disposed on the second active region.

Abstract: An image capturing device is provided. The device includes a substrate comprising a pixel region, a peripheral region and a trench region, in which trenches are formed, between the pixel region and the peripheral region. The plurality of trenches include first trenches arranged to be spaced apart from each other in a first direction along a first side of an outer edge of the pixel region and second trenches arranged to be spaced apart from each other in the first direction. The first and second trenches are arranged to be spaced apart from each other in a second direction crossing the first direction. The first and second trenches are arranged so that, any straight line path which connects, without overlapping any one of the first and second trenches, the first side and the peripheral region, does not exist.

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.

Abstract: The present disclosure provides a display panel having a stress releasing structure and a method for manufacturing the same. The display panel having a stress releasing structure includes a substrate having a display area, a bending area, and a peripheral area, wherein the bending area is positioned between the display area and the peripheral area; a metal wiring disposed on the substrate and extending from the display area to the peripheral area; a planarization layer positioned in the bending area and disposed on the metal wiring; and a pixel defining layer positioned in the bending area and disposed on the planarization layer; wherein at least one of the planarization layer and the pixel defining layer includes a plurality of semi-columns parallel to each other.

Abstract: An image sensor includes a substrate having a plurality of pixel regions, a lower layer on the substrate; a plurality of color filters on the lower layer, and a micro-lens layer on or covering top surfaces of the color filters. The micro-lens layer extends to a location between two of the color filters and contacts the lower layer on one of the pixel regions. The color filters are spaced apart from the lower layer.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a memory cell, a first logic transistor, and a second logic transistor. The semiconductor substrate includes a memory region and a logic region. The memory cell is disposed in the memory region. The first logic transistor is disposed in the memory region and disposed adjacent to the memory cell. The second logic transistor is disposed in the logic region. The first logic transistor is configured to control operation of the memory cell in response to a memory control signal provided by the second logic transistor.

Abstract: A display device includes a plurality of pixels, first to nth scanning lines, and a first semiconductor film. The plurality of pixels is arranged in first to nth rows and first to mth columns. The first to nth scanning lines are electrically connected to the pixels in the respective first to nth rows. The first semiconductor film overlaps with at least one of first to kth scanning lines. A display region has a cutoff intersecting the first to nth rows, and the first semiconductor film is located in the cutoff. Each of the plurality of pixels includes a light-emitting element (OLED) and a transistor electrically connected to the OLED and having a second semiconductor film. The first semiconductor film and the second semiconductor film exist in the same layer. n and m are each a natural number larger than 1, and k is a natural number smaller than n.

Abstract: A stretchable display panel having a plurality of encapsulated islands and a plurality of bridges connecting the plurality of encapsulated islands. The stretchable display panel includes a plurality of light emitting elements. A respective one of the plurality of encapsulated islands includes at least one of the plurality of light emitting elements encapsulated therein on a base substrate. A respective one of the plurality of light emitting elements includes a first electrode, a light emitting layer on the first electrode, and a second electrode on a side of the light emitting layer away from the first electrode. The stretchable display panel further includes a plurality of connecting lines connecting second electrodes of the plurality of light emitting elements respectively through the plurality of bridges. The plurality of connecting lines include a material different from a material of the second electrode.

Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a conformal dielectric encapsulation liner is located on a sidewall of each of a MTJ pillar and an overlying top electrode, and a non-conformal dielectric encapsulation liner is located on the conformal dielectric encapsulation liner. This dual encapsulation liner structure prevents the bottom electrode of the MTJ containing device from being physically exposed thus eliminating the possibility that the bottom electrode can be a source of resputtered conductive metal particles that can deposit on a sidewall of the MTJ pillar. As such, electrical shorting is reduced in the MTJ containing device of the present application. Also, the dual encapsulation liner structure can mitigate chemical diffusion into the tunnel barrier material of the MTJ pillar.