Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: A light-emitting diode includes: a light emitting epitaxial structure including a first-type semiconductor layer, an active layer and a second-type semiconductor layer, and having a first surface as a light emitting surface, and an opposing second surface; a conducting layer formed over the second surface and including a physical plating layer and a chemical plating layer, wherein the physical plating layer is adjacent to the light emitting epitaxial structure and has cracks, and the chemical plating layer fills the cracks in the physical plating layer; and a submount coupled to the light emitting epitaxial laminated layer through the conducting layer.

Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.

Abstract: A semiconductor device and a fabrication method are provided. The method includes forming a first fin structure and a second fin structure on a substrate. The first fin structure includes a first sidewall surface, facing to the second fin structure, and a second sidewall surface opposite to the first sidewall surface. The method also includes forming an isolation layer to cover a portion of sidewall surfaces of the first fin structure and the second fin structure. The top surface of the isolation layer is lower than the top surfaces of the first fin structure and the second fin structure. The method further includes forming a first sidewall on the first sidewall surface; forming a first doped layer in the first fin structure; and forming a second doped layer in the second fin structure. The first sidewall covers a portion of a sidewall surface of the first doped layer.

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

Abstract: A display panel is provided. The display panel includes: a flexible substrate including a display area and a non-display area; a thin film transistor layer formed on the flexible substrate; grooves formed in the thin film transistor layer corresponding to the non-display area; a planarization layer and a pixel definition layer disposed on the thin film transistor layer respectively; bumps formed in the non-display area after patterning the planarization layer and the pixel definition layer; and a light emitting layer and a thin film encapsulation layer formed on the planarization layer in order, wherein the thin film encapsulation layer covers the bumps and the grooves.

Abstract: A magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a tunnel barrier layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer is an oxide having a spinel structure, and the tunnel barrier layer includes a magnetic element as an additional element.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.

Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.

Abstract: An optoelectronic component includes a housing including a first cavity bounded by a first wall, wherein a circumferentially extending first step is formed at an inner side of the first wall, the first step circumferentially extends around the first cavity obliquely with respect to a bottom of the first cavity, a first optoelectronic semiconductor chip is arranged at the bottom of the first cavity, the first optoelectronic semiconductor chip is embedded into a first potting material arranged in the first cavity and extending from the bottom of the first cavity as far as the first step, and a first potting surface of the first potting material is formed at the first step.

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.

Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, a multi-layer stack is formed and patterned to form a hard mask, a top electrode and a resistance switching dielectric. Then, a first dielectric spacer layer is formed over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask. Then, a second dielectric spacer layer is formed directly on and conformally lining the first dielectric spacer layer. The first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.

Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface and a back surface, at least one semiconductor device, a first TSV disposed in the substrate, an insulating layer surrounding the first TSV, a shielding layer surrounding the insulating layer, and a second TSV adjacent to the first TSV. The semiconductor device is disposed in a device region of the substrate. The first TSV is exposed by the front surface and the back surface of the substrate. The insulating layer includes an electrically insulating material. The shielding layer includes an electrically conductive material coupled to ground through a ground layer. The second TSV is exposed by the front surface and the back surface of the substrate.

Abstract: A display device includes: a central area having a display area on a substrate; and a peripheral area around the central area; a plurality of pads arranged along one direction in the central area; a plurality of insulating patterns adjacent the plurality of pads; and a slit between the plurality of insulating patterns in the peripheral area, wherein the slit is formed by removing at least a portion of an insulating material of the plurality of insulating patterns.