Patents Examined by Dzung Tran
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Patent number: 11114477Abstract: In a method for manufacturing an array substrate, a first photoresist pattern is formed on a buffer layer of a non-display region and the buffer layer uncovered by the first photoresist pattern is removed to form a first via hole in the non-display region. A second via hole is formed on the basis of the first via hole. The second via hole is connected to the first via hole. By forming the first via hole in the non-display region and forming the second via hole on the basis of the first via hole, completeness of film layers is ensured and product yield is improved.Type: GrantFiled: August 23, 2018Date of Patent: September 7, 2021Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventors: Caiqin Chen, Xing Ming
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Patent number: 11101244Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.Type: GrantFiled: May 18, 2020Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Seng Kim Ye, Hong Wan Ng
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Patent number: 11101330Abstract: Disclosed is an electroluminescent display device comprising a substrate, a circuit device layer including a signal line on the substrate, a bank defining a first emission area and a second emission area on the circuit device layer, and a first emission layer in the first emission area, and a second emission layer in the second emission area, wherein the first emission area is overlapped with the signal line, and a width of the first emission area is the same as or less than a width of the signal line.Type: GrantFiled: June 24, 2020Date of Patent: August 24, 2021Assignee: LG DISPLAY CO., LTD.Inventors: EunJi Park, Sungman Han, Kihyung Lee
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Patent number: 11101262Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.Type: GrantFiled: November 8, 2019Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Hong Wan Ng, Seng Kim Ye
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Patent number: 11101294Abstract: An array substrate includes pixel electrodes, switching components, a line, a common electrode, and a common line. The switching components are connected to the pixel electrodes. The line is connected to the switching components. The common electrode includes common electrode segments provided for the pixel electrodes, respectively. The common electrode segments are disposed to overlap at least sections of the pixel electrodes, respectively, via an inter-electrode insulator but not to overlap the line. The common line extends to straddle the common line segments. The common line is connected to the common electrode segments. The common line is a section of a conductive film that includes a section configured as the line.Type: GrantFiled: October 17, 2019Date of Patent: August 24, 2021Assignee: SHARP KABUSHIKI KAISHAInventor: Masahiro Yoshida
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Patent number: 11094359Abstract: A magnetic memory pillar structure having a plurality of magnetic memory elements connected in series, wherein switching of individual memory elements in the pillar structure can be accomplished based on differing switching current values of the magnetic memory elements. Each of the plurality of memory elements advantageously have similar retention values in spite of the different switching current values (latency values) as a result of a precessional spin current injection structure provided in the memory element or memory elements having the lower switching current value.Type: GrantFiled: January 24, 2019Date of Patent: August 17, 2021Assignee: SPIN MEMORY, INC.Inventors: Kadriye Deniz Bozdag, Mustafa Pinarbasi
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Patent number: 11094795Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a gate electrode, a drain region, a source region, an isolating layer, a plurality of metal contacts, a plurality of conductive plugs, and a contact liner. The gate electrode is disposed on the substrate. The drain region and the source region are disposed in the substrate and on opposite sides of the gate electrode. The isolating layer is disposed over the substrate and the gate electrode. The metal contacts are disposed in the gate electrode, the source region, and the drain region. The conductive plugs are disposed in the isolating layer and electrically coupled to the metal contacts. The contact liner surrounds the conductive plugs. The present disclosure further provides a method for manufacturing the semiconductor device.Type: GrantFiled: July 1, 2019Date of Patent: August 17, 2021Assignee: Nanya Technology CorporationInventor: Chun-Shun Huang
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Patent number: 11087831Abstract: Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.Type: GrantFiled: August 22, 2019Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Jhon Jhy Liaw
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Patent number: 11081411Abstract: A semiconductor structure (100; 200) is provided.Type: GrantFiled: August 12, 2019Date of Patent: August 3, 2021Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBHInventor: Matthias Pittner
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Patent number: 11081353Abstract: A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.Type: GrantFiled: October 29, 2018Date of Patent: August 3, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Yu-Cheng Tung
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Patent number: 11081530Abstract: A pixel arrangement structure, a display panel, a mask component, and an evaporation apparatus are provided. The pixel arrangement structure includes a plurality of sub-pixels arranged in a row direction and a column direction. The plurality of sub-pixels are divided into a plurality of rows of sub-pixel groups. Each of rows of sub-pixel groups include at least two rows of the sub-pixels, and include a plurality of repeating units arranged in sequence, and each of the repeating units includes at least two sub-pixel groups of different colors. Each of the sub-pixel groups includes at least two sub-pixels of a same color that are located in at least two rows and are adjacently arranged, and sub-pixels adjacent to each other and having different colors, which are located in sub-pixel groups of different colors, constitute one pixel.Type: GrantFiled: April 12, 2019Date of Patent: August 3, 2021Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventor: Yuanqi Zhang
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Patent number: 11075219Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.Type: GrantFiled: August 20, 2019Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Xiaosong Zhang, Yi Hu, Tom J. John, Wei Yeeng Ng, Chandra Tiwari
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Patent number: 11075307Abstract: Embodiments of the invention are directed to a method of fabrication of an electro-optical device. A non-limiting example of the method relies on a waveguide. A trench is opened in the waveguide and a stack of optically active semiconductor materials is directly grown from a bottom wall of the trench and are stacked along a stacking direction that is perpendicular to a main plane of the waveguide. The stack is partly encapsulated in the waveguide, whereby a bottom layer of the stack is in direct contact with a waveguide core material, whereas upper portions of opposite, lateral sides of the stack are exposed. An insulating layer of material is deposited to cover exposed surfaces of the waveguide and structured to form a lateral growth template. Contact layers are laterally grown due to the lateral growth template formed. The contact layers can include an n-doped and p-doped contact layers.Type: GrantFiled: July 18, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles Caër, Yannick Baumgartner, Lukas Czornomaz
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Patent number: 11075303Abstract: An oxide semiconductor compound includes gallium; and oxygen. An optical band gap is 3.4 eV or more. An electron Hall mobility obtained by performing a Hall measurement at a temperature of 300 K is 3 cm2/Vs or more.Type: GrantFiled: August 30, 2018Date of Patent: July 27, 2021Assignees: TOKYO INSTITUTE OF TECHNOLOGY, AGC Inc.Inventors: Hideo Hosono, Toshio Kamiya, Hideya Kumomi, Junghwan Kim, Nobuhiro Nakamura, Satoru Watanabe, Naomichi Miyakawa
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Patent number: 11069615Abstract: An inductor includes: a substrate; a first wiring line located on the substrate; a second wiring line located above the first wiring line and spaced from the first wiring line through an air gap, at least a part of the second wiring line overlapping with at least a part of the first wiring line in plan view; a first supporting post connecting ends of the first and second wiring lines such that a direct current conducts between the first and second wiring lines through the first supporting post; and a second supporting post provided such that the second supporting post overlaps with the second wiring line in plan view, and overlaps with the first wiring line in plan view or is surrounded by the first wiring line in plan view, the second supporting post being insulated from the first wiring line, the second supporting post supporting the second wiring line.Type: GrantFiled: October 17, 2019Date of Patent: July 20, 2021Assignee: TAIYO YUDEN CO., LTD.Inventors: Takeshi Sakashita, Takashi Matsuda
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Patent number: 11069683Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.Type: GrantFiled: September 26, 2019Date of Patent: July 20, 2021Assignee: ICs LLCInventors: Sterling Whitaker, Gary Maki
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Patent number: 11069674Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.Type: GrantFiled: August 12, 2019Date of Patent: July 20, 2021Assignee: INFINEON TECHNOLOGIES AGInventor: Joost Adriaan Willemen
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Patent number: 11063184Abstract: A light-emitting diode includes: a light emitting epitaxial structure including a first-type semiconductor layer, an active layer and a second-type semiconductor layer, and having a first surface as a light emitting surface, and an opposing second surface; a conducting layer formed over the second surface and including a physical plating layer and a chemical plating layer, wherein the physical plating layer is adjacent to the light emitting epitaxial structure and has cracks, and the chemical plating layer fills the cracks in the physical plating layer; and a submount coupled to the light emitting epitaxial laminated layer through the conducting layer.Type: GrantFiled: September 20, 2018Date of Patent: July 13, 2021Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chao Jin, Chuang Yu Hsieh, Chen Kang Hsieh, Duxiang Wang, Chaoyu Wu, Chih Pang Ma
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Patent number: 11061146Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.Type: GrantFiled: January 24, 2019Date of Patent: July 13, 2021Assignee: International Business Machines CorporationInventors: Jeng-Bang Yau, Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari
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Patent number: 11063052Abstract: A semiconductor device and a fabrication method are provided. The method includes forming a first fin structure and a second fin structure on a substrate. The first fin structure includes a first sidewall surface, facing to the second fin structure, and a second sidewall surface opposite to the first sidewall surface. The method also includes forming an isolation layer to cover a portion of sidewall surfaces of the first fin structure and the second fin structure. The top surface of the isolation layer is lower than the top surfaces of the first fin structure and the second fin structure. The method further includes forming a first sidewall on the first sidewall surface; forming a first doped layer in the first fin structure; and forming a second doped layer in the second fin structure. The first sidewall covers a portion of a sidewall surface of the first doped layer.Type: GrantFiled: August 9, 2019Date of Patent: July 13, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation Shanghai, China, Semiconductor Manufacturing International (Beijing) Corporation Beijing, ChinaInventor: Fei Zhou
