Abstract: A semiconductor device includes a substrate, a dielectric fin, a gate, and a high-k dielectric layer. The dielectric fin is above the substrate and extending along a first direction. The gate is above the substrate and extends in a second direction that intersects the first direction. The high-k dielectric layer is vertically above the dielectric fin. The gate is over a sidewall and a bottom surface of the high-k dielectric layer.

Abstract: In one embodiment, there is provided a display substrate including: a base substrate; a plurality of pixels on the base substrate; and a pixel definition layer on the base substrate, defining the pixels and separating the pixels from one another. Each of the pixels includes: a first electrode assembly, a light-emitting function layer and a second electrode arranged sequentially in a direction away from the base substrate, and the second electrodes of the pixels form a common electrode layer extending over the pixel definition layer. In each of the pixels, a distance between a surface of the pixel definition layer away from the base substrate and a surface of the light-emitting function layer away from the base substrate in the direction away from the base substrate is less than or equal to a preset threshold that is in a range of about 0 ? to about 300 ?.

Abstract: Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices.

Abstract: A mobile body=includes a reflection control layer that is formed on a surface of the mobile body, to absorb light in a wavelength region from 0.3 micrometer to 0.75 micrometer of incident sunlight, and emit light in a wavelength region from 0.75 micrometer to 100 micrometers.

Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.

Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a first P-type transistor including a first SiGe channel region, and a second P-type transistor including a second SiGe channel region. The first SiGe channel region has higher Ge atomic concentration than the second SiGe channel region. The first and second P-type transistors are formed in the same N-type well region.

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.

Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

Abstract: Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

Abstract: A 3D printed display panel includes two opposing substrates and a black matrix formed on one of the substrates. The light proof areas of the black matrix include multiple first portions, multiple second portions and multiple third portions arranged to form a grid structure. The first portions and the third portions are alternately arranged in a direction of the scanning lines, the second portions and the third portions are alternately arranged in a direction of the data lines. Meshes of the grid structure are aperture zones of the black matrix. The aperture zones are in one-to-one correspondence with the pixel units. A vertical projections of the scanning lines and the data lines on the second substrate are located in the lightproof areas; where a minimum width of one first portion is X, a minimum width of one second portion is Y, and |X?Y|?2 ?m.

Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

Abstract: The present disclosure provides a semiconductor device and a method for forming the semiconductor device. The method includes forming a first conductive structure over a substrate, forming a first dielectric structure over the first conductive structure, transforming a sidewall portion of the first conductive structure into a first dielectric portion, removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive structure.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.

Abstract: A method of manufacturing a composite film layer applicable to a flexible display panel includes providing a transparent substrate film; forming a deformed state of the transparent substrate film by applying a predetermined degree of tensile stress to the transparent substrate film; forming a hardened layer on the transparent substrate film in the deformed state; and releasing the tensile stress from the transparent substrate film in the deformed state to enable a molecular chain in the hardened layer to contract.

Abstract: Disclosed are methods and apparatus pertaining to processing in-situ, real-time data associated with fluid obtained by a downhole sampling tool. The processing includes generating a population of values for ?, where each value of ? is an estimated value of a fluid property for native formation fluid within the obtained fluid. The obtained data is iteratively fit to a predetermined model in linear space. The model relates the fluid property to pumpout volume or time. Each iterative fitting utilizes a different one of the values for ?. A value ?* is identified as the one of the values ? that minimizes model fit error in linear space based on the iterative fitting. Selected values ? that are near ?* are then assessed to determine which one has a minimum integral error of nonlinearity in logarithmic space.

Abstract: Disclosed is in the embodiment is a semiconductor device comprising: a first conductive semiconductor layer; a second conductive semiconductor layer; an active layer disposed between the second conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer includes a first sub semiconductor layer, a third sub semiconductor layer and a second sub semiconductor layer disposed between the first sub semiconductor layer and the third sub semiconductor layer, wherein proportion of aluminum in the first sub semiconductor layer and the third sub semiconductor layer is larger than an proportion of aluminum in the active layer, and an proportion of aluminum in the second sub semiconductor layer is smaller than the proportion of aluminum in the first sub semiconductor layer and the

Abstract: A photodiode has an absorption layer and a cap layer operatively connected to the absorption layer. A pixel is formed in the cap layer and extends into the absorption layer to receive charge generated from photons therefrom. The pixel defines an annular diffused area to reduce dark current and capacitance. A photodetector includes the photodiode. The photodiode includes an array of pixels formed in the cap layer. At least one of the pixels extends into the absorption layer to receive charge generated from photons therefrom. At least one of the pixels defines an annular diffused area to reduce dark current and capacitance.

Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.