Abstract: A flow metering apparatus comprising a temperature sensing system for use to measure temperature of fluid includes temperature measurement components and temperature sensing components in close proximity to one another and to the flow of fluid. The components can include a temperature measurement member close-coupled to a processor member, each disposed on a circuitized substrate. This configuration exposes a temperature sensor element to the same dynamic temperature conditions as the processor member, thus reducing measurement error that might manifest in response to different temperature gradients proximate the respective components. A storage memory may be used to permit the temperature sensing system to store and/or retain data that relates to calibration as a dynamic system over the entire operating range of the sensor element. The calibration data may then be accessed from the storage memory to improve accuracy and operation of the flow metering apparatus.

Abstract: The present disclosure relates to a system for sourcing and sinking power. The system may have a bi-directional system of electrical components configured for placement in electrical communication with a power source and a load. The bi-directional system may further be configured to source AC and DC power from the power source to the load and sink AC and DC power from the load to the power source. The system may further include a high frequency isolation transformer. In some embodiments, the system may have four input/output channels. The bi-directional system of electrical components may include a line filter configured to reduce harmonic content, a line converter configured for converting between AC power and DC power, a load converter configured for converting between AC power and DC power, and a load filter configured to reduce harmonic content.

Abstract: An organic light emitting display device is disclosed. The organic light emitting display device includes a first light emitting part between an anode and a cathode, the first light emitting part having a first light emitting layer, and a second light emitting part between the first light emitting part and the cathode, the second light emitting part having a second light emitting layer and a third light emitting layer, wherein the second light emitting layer includes a hole-type host and a first electron-type host, and the third light emitting layer includes a first electron-type host and a second electron-type host.

Abstract: A thin film transistor substrate that includes a substrate, a lower gate electrode arranged on the substrate, a semiconductor layer arranged on the substrate and overlapping the lower gate electrode, the semiconductor layer including a channel region interposed between a source region and a drain region, and an upper gate electrode arranged on the substrate and overlapping the semiconductor layer, the upper gate electrode being arranged on an opposite side of the semiconductor layer than the lower gate electrode, wherein at least one of the lower gate electrode and the upper gate electrode is perforated by an aperture to reduce a parasitic capacitance between the upper and lower gate electrodes.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

Abstract: A method for manufacturing a three-dimensional (3D) memory structure and a 3D memory structure are disclosed. A recess is formed on a substrate, a 3D memory component is formed with a bottom in the recess, and then, a peripheral circuit is formed on the substrate outside the recess.

Abstract: A light emitting device includes a first light emitting cell, a second light emitting cell, a first conductive pattern, a second conductive pattern, and a connection pattern. The connection pattern includes contact portions electrically connected to a second conductivity type semiconductor layer of the first light emitting cell and a first conductivity type semiconductor layer of the second light emitting cell. At an edge of a first region facing the second light emitting cell, one contact portion of the first conductive pattern is disposed between the contact portions of the connection pattern electrically connected to the second conductivity type semiconductor layer of the first light emitting cell, and one contact portion of the first conductive pattern is open outwards.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

Abstract: Provided are a thin film transistor substrate and a display using the same. A display includes: a first area, a second area, a first thin film transistor disposed at the first area, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed at the second area, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode, and an oxide layer disposed over the first gate electrode and the second gate electrode.

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: An organic semiconductor element functions as a strain sensor, and includes a substrate and an organic semiconductor layer formed on the substrate as a single-crystal thin film of an organic semiconductor that is a polycyclic aromatic compound with four or more rings or a polycyclic compound with four or more rings including one or a plurality of unsaturated five-membered heterocyclic compounds and a plurality of benzene rings. Since the organic semiconductor layer is formed as the single-crystal thin film, an identical crystal structure is obtained regardless of formation technique. Therefore, when the same strain is given, the same carrier mobility is obtained and uniform property is obtained with respect to the strain. Accordingly, it is possible to provide strain sensors having uniform property.

Abstract: A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having first and second plane, a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region between the first semiconductor region and the first plane, a first conductivity-type third semiconductor region between the second semiconductor region and the first plane, a second conductivity-type fourth semiconductor region between the third semiconductor region and the first plane, a first conductivity-type fifth semiconductor region provided between the first semiconductor region and the first plane, a first electrode provided on a side of the first plane, and electrically connected to the third semiconductor region and the fourth semiconductor region, a second electrode provided on a side of the second plane, and electrically connected to the first semiconductor region, and a conductive layer provided on a side of the first plane, and electrically connecting the second and the fifth s

Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.