Abstract: Methods and systems associated with data modification are described. Examples can include receiving, at a controller of a device, data associated with a read or write command transmitted to a memory resource and modifying the data using logic before transmitting the data to a host or image sensor or before writing the data to the memory resource. The modification can include removing one or more bits from the data, reordering one or more bits of the data, changing a format of the data, or any combination thereof. The modified data can be transmitted to the host or image sensor or written to the memory resource. In some examples, a plurality of memory devices can combine modified data for transmitting to a host.

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

Abstract: A computing-in-memory circuit includes a Resistive Random Access Memory (RRAM) array and a peripheral circuit. The RRAM array comprises a plurality of memory cells arranged in an array pattern, and each memory cell is configured to store a data of L bits, L being an integer not less than 2. The peripheral circuit is configured to, in a storage mode, write more than one convolution kernels into the RRAM array, and in a computation mode, input elements that need to be convolved in a pixel matrix into the RRAM array and read a current of each column of memory cells, wherein each column of memory cells stores one convolution kernel correspondingly, and one element of the convolution kernel is stored in one memory cell correspondingly, and one element of the pixel matrix is correspondingly input into a word line that a row of memory cells connect.

Abstract: A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application thread to indicate an undo logging operation when calculations are beginning that may need to be rolled back if a crash or other failure occurs. During the undo logging operation, memory writes an identified memory are done to a copy and the original value is preserved. If the undo logging operation is committed, then the copy becomes the correct value and may then be subsequently used in place of the original, or the value stored in the copy is copied to the original. If the undo logging operation is abandoned, the copy is not preserved and the value goes back to the original.

Abstract: A system and method of adding a high-rate channel to a legacy baseband bus includes a bus communicatively coupled to a transmitter and a receiver via one or more transformer couplers, where the transmitter and receiver transmit and receive a first signal over the bus utilizing a differential mode. The system also includes at least two modems coupled to the bus, where a first modem transmits a second signal over the bus for receipt by a second modem, where the at least two modems are each coupled to the bus via the one or more transformer couplers, where the second signal is transmitted over the bus utilizing a common mode, and where the first signal and the second signal are spatially separated on the bus based on an isolation between the common mode and the differential mode.

Abstract: Methods for local page writes via pre-staging buffers for resilient buffer pool extensions are performed by computing systems. Compute nodes in database systems insert, update, and query data pages maintained in storage nodes. Data pages cached locally by compute node buffer pools are provided to buffer pool extensions on local disks as pre-copies via staging buffers that store data pages prior to local disk storage. Encryption of data pages occurs at the staging buffers, which allows a less restrictive update latching during the copy process, with page metadata being updated in buffer pool extensions page tables with in-progress states indicating it is not yet written to local disk. When stage buffers are filled, data pages are written to buffer pool extensions and metadata is updated in page tables to indicate available/valid states. Data pages in staging buffers can be read and updated prior to writing to the local disk.

Abstract: In one example, an apparatus comprises: a local on-chip memory; a computation engine configured to generate local data and to store the local data at the local on-chip memory; and a controller. The apparatus is configured to be coupled with a second device via an interconnect, the second device comprising a local memory. The controller is configured to: fetch the local data from the local on-chip memory; fetch remote data generated by another device from a local off-chip memory; generate output data based on combining the local data and the remote data; and store, via the interconnect, the output data at the local memory of the second device.

Abstract: A system and methods for enhancing content collaboration by conflict detection and resolution. A hybrid cloud cache receives a request from a client to upload an object to the cloud. The hybrid cloud cache may perform an internal lookup to find the latest version of the object known to it. This lookup may return a local identifier or a cloud identifier. The cache may compare a client-provided identifier to the local identifier or to the cloud identifier that is mapped to the local identifier to determine if the client-provided identifier refers to the latest uploaded version of the object. The system may determine that a conflict exists if the client-provided identifier does not match either identifier. The system may generate an alternate name for the object and upload the renamed object to the cloud from the hybrid cloud cache.

Abstract: Maximizing data throughput in a cloud-based storage system, including: receiving a plurality of write operations directed to a cloud-based storage system; coalescing the plurality of write operations into one or more coalesced write operations, wherein each of the coalesced write operations are configured to effect two or more of the first plurality of write operations; and performing, based on a service tier associated with the cloud-based storage system, the plurality of coalesced write operations on the storage volume.

Abstract: A fault-tolerant data storage system associates durability requirements of service level agreements (SLAs) for volumes stored in the fault-tolerant data storage system with volume partitions stored in the fault-tolerant data storage system. For a given volume partition, volume data is stored in two or more replicas on two or more different system components and/or erasure encoded across multiple other system components. The fault-tolerant data storage system uses the respective durability requirements of the SLAs and failure statistics of the system components to allocate bandwidth for replacing lost instances of redundantly stored volume data such that the lost data is replaced within a target time calculated to guarantee the durability requirements of the SLAs are satisfied.

Abstract: A data storage apparatus and method and a readable storage medium are provided. The data storage apparatus includes: a processor and a memory; the processor includes: a buffer scheduler, a plurality of transmission buffers, an interface buffer, and a memory controller; the buffer scheduler is configured to control the plurality of transmission buffers to write data, and read out the data and send the data to the interface buffer; the interface buffer is configured to receive data sent by the transmission buffers if a capacity of data stored in the interface buffer is less than a preset capacity threshold, and stop receiving data sent by the transmission buffers if the capacity of data stored in the interface buffer is greater than or equal to the preset capacity threshold; and the memory controller is configured to control the memory to write data from the interface buffer and store the data.

Abstract: Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.

Abstract: An electronic control unit includes an installation execution unit that operates at least one of an application program or parameter data stored in a first data storage bank serving as an active bank and rewrites a second data storage bank serving as an inactive bank by writing, to the second data storage bank, update data acquired from an external device, and an activation execution unit that switches the active bank from the first data storage bank to the second data storage bank. The installation execution unit rewrites the second data storage bank during a vehicle being travelable or parked. The activation execution unit switches the active bank from the first data storage bank to the second data storage bank during the vehicle being parked.

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

Abstract: Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.

Abstract: A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.