Abstract: A method and system for capturing asset protection metadata pertinent to analytics. Specifically, the disclosed method and system entail aggregating and maintaining asset protection metadata—i.e., metadata descriptive of performed asset backup and recovery operations—in a central location. The asset protection metadata may include information relevant to backup and recovery analytics and reporting, while the maintaining said metadata in the central location facilitates access of the metadata by third-party analytics services.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: Systems and methods for time control for a data interface between a source device and a receiving device are provided. In one example, a method can include performing a capture time sweep process at the receiving device. The capture time sweep process includes performing a plurality of test data transfers at the receiving device at a plurality of different capture time settings. The method can include determining a capture time window based at least in part on the capture time sweep process. The capture time window can be defined as a duration between a first capture time and a second capture time. The method can include determining a selected capture time between the first capture time and the second capture time. The method can include controlling data transfer across the data interface based at least in part on the selected capture time.

Abstract: Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Abstract: Monitoring and reporting methods and apparatus include the acquisition of detailed aircraft state and systems data, analysis of the collected data, and transmission of the collected data and/or analysis of the collected data to a destination automatically via a portable electronic device which is carried onto and off of the aircraft by the pilot or another crew member. More particularly, monitoring and reporting methods and apparatus include collecting analog or digital sensor data onboard an aircraft, analyzing the data in real-time, and automatically transmitting the data and/or analysis of the data to a destination including a portable storage device such as a portable computer, electronic flight bag (EFB), or smart phone, by means such as wireless transmission, for automatic transfer to another destination when the portable computer, electronic flight bag (EFB), or smart phone is off of the aircraft.

Abstract: A memory system includes: a plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller through a channel; a super block including pages included in the planes of at least two memory devices among the plurality of memory devices; and the memory controller for transmitting, to the memory devices, at least one command instructing an operation on the super block and an address corresponding to the command. Each of the memory devices includes: peripheral circuit for performing the operation on the memory cell array; a group selection signal generator for outputting a group selection signal indicating the at least two memory devices constituting the super block; and control logic for controlling the peripheral circuit to perform an operation corresponding to the command, based on the group selection signal.

Abstract: A priority queue sorting system including a priority queue and a message storage. The priority queue includes multiple priority blocks that are cascaded in order from a lowest priority block to a highest priority block. Each priority block includes a register block storing an address and an identifier, compare circuitry that compares a new identifier with the stored identifier for determining relative priority, and select circuitry that determines whether to keep or shift and replace the stored address and identifier within the priority queue based on the relative priority. The message storage stores message payloads, each pointed to by a corresponding stored address of a corresponding priority block. Each priority block contains its own compare and select circuitry and determines a keep, shift, or store operation. Thus, sorting is independent of the length of the priority queue thereby achieving deterministic sorting latency that is independent of the queue length.

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

Abstract: Exemplary methods, apparatuses, and systems include receiving a plurality of read operations directed to a portion of memory accessed by a memory channel. The plurality of read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A supplemental memory location is selected independently of aggressors and victims in the current set of read operations. A first data integrity scan is performed on a victim of the aggressor read operation and a second data integrity scan is performed on the supplemental memory location.

Abstract: Methods and systems associated with data modification are described. Examples can include receiving, at a controller of a device, data associated with a read or write command transmitted to a memory resource and modifying the data using logic before transmitting the data to a host or image sensor or before writing the data to the memory resource. The modification can include removing one or more bits from the data, reordering one or more bits of the data, changing a format of the data, or any combination thereof. The modified data can be transmitted to the host or image sensor or written to the memory resource. In some examples, a plurality of memory devices can combine modified data for transmitting to a host.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: A system comprises a communications module; a processor coupled to the communications module; and a memory coupled to the processor, the memory storing processor-executable instructions which, when executed by the processor, configure the processor to receive, via the communications module, a transfer instruction for transfer of data from a first data record associated with a transferor to a second data record associated with a recipient, the transfer instruction including a transfer amount and a condition associated with the transfer; send, via the communications module, a notification of the transfer instruction to a computing device associated with the recipient and request permission to obtain contextual data therefrom; when permission is granted, obtain, via the communications module, contextual data from the computing device; determine, based on the contextual data, that the condition associated with the transfer has been satisfied; and in response to determining that the condition associated with the t

Abstract: In one example, an apparatus comprises: a local on-chip memory; a computation engine configured to generate local data and to store the local data at the local on-chip memory; and a controller. The apparatus is configured to be coupled with a second device via an interconnect, the second device comprising a local memory. The controller is configured to: fetch the local data from the local on-chip memory; fetch remote data generated by another device from a local off-chip memory; generate output data based on combining the local data and the remote data; and store, via the interconnect, the output data at the local memory of the second device.

Abstract: A memory controller having improved reliability and performance controls an operation of a memory device. The memory controller includes a first core configured to receive requests from a host, each request received with a corresponding first logical address associated with data requested from the host and having a first size, and to perform a logical address processing operation of converting the first logical address into a second logical address having a second size different from the first size; and a second core configured to convert the second logical address into a physical address to or from which the data is to be written or read, the physical address representing a position of a memory cell included in the memory device.

Abstract: An apparatus includes multiple computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple coprocessors associated with each computing core, where each coprocessor is configured to receive the input data from at least one of the computing cores, process the input data, and generate output data. The apparatus further includes multiple reducer circuits, where each reducer circuit is configured to receive the output data from each of the coprocessors of an associated computing core, apply one or more functions to the output data, and provide one or more results to the associated computing core. In addition, the apparatus includes multiple communication links communicatively coupling the computing cores and the coprocessors associated with the computing cores.

Abstract: Systems for managing thermal dissipation in multi-stacked memory dies, and methods and computer-readable storage media related thereto, are provided. The system includes memory dies including memory blocks to store data. A processing component is configured to maintain memory block states for the memory blocks. The memory block states include: an open memory block state allowing write operations, and a closed memory block state preventing write operations. The processing component is further configured to: receive a first write command to store first data, and compute first relative distances between open memory blocks in the open memory block state. The processing component is further configured to: select a set of open memory blocks for a first write operation based on the first relative distances so as to manage thermal dissipation, and initiate the first write operation on the first set of open memory blocks.

Abstract: Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: An electronic device includes a first controller compliant with a first storage standard, a second controller compliant with a second storage standard, a switching unit that switches setting information between first setting information corresponding to the first storage standard and second setting information corresponding to the second storage standard, and a connection establishing unit that executes processing of establishing connection between an external storage device and one of the first controller or the second controller, the one of the first controller or the second controller compliant with the setting information set by the switching of the switching unit.

Abstract: A memory system includes a memory device configured to store a piece of data in a location which is distinguished by a physical address and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to transfer a response including the piece of map data to the external device.