Abstract: A single-wire bus apparatus that includes a bus slave circuit(s) is provided. The bus slave circuit(s) can receive a unicast, a multicast, and/or a broadcast command sequence over a single-wire bus. In embodiments disclosed herein, the bus slave circuit(s) can be configured to determine whether to respond to a received multicast or broadcast command sequence based on a predefined response policy. As such, the single-wire bus apparatus can be configured to mix and match a legacy slave circuit(s), which always responds to the received multicast or broadcast command sequence, with an enhanced slave circuit(s) that can decide whether to respond to the received multicast or broadcast command sequence based on the predefined response policy. As a result, it is possible to improve design and implementation flexibility, such as supporting more bus slave circuits per port.

Abstract: A method to transfer an artificial intelligence (AI) model includes identifying a plurality of layers of an AI model, wherein each layer of the plurality of layers is associated with a memory address. The method further includes randomizing the memory address associated with each layer of the plurality of layers, and transferring the plurality of layers with the randomized memory addresses to a data processing accelerator to execute the AI model.

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

Abstract: Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Abstract: A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.

Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

Abstract: This application describes a system startup method and apparatus. The method may include establishing a mapping relationship between address space of a first storage device and address space of a second storage device. The method may also include receiving a read/write request sent to the first storage device. Furthermore, the method may include when the read/write request is a write request for the first storage device, writing data to a second address in the second storage device based on a first address in the first storage device in the write request and the mapping relationship. Or, when the read/write request is a read request for the first storage device, determining whether data has been written to a fourth address corresponding to a third address in the read request. The method may further include reading data from the fourth address when the data has been written to the fourth address, or reading data from the third address when no data has been written to the fourth address.

Abstract: Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.

Abstract: The technology describes synchronization of writer and reader applications in a streaming data storage system, such as to facilitate a mode switch in which event writers can change event contents being appended to stream segments and event readers can process the event contents according to the new mode. A signal event is generated by a signaler for stream segments to which data event writes are being written, which changes the data writers' writing mode. The data storage system rejects appends of events after the signal that do not correspond to the new writing mode. The data storage system also writes a signal indicator to the segments being read at a location in each segment that is between the events written before the signal and the events written after the signal. Reader applications are synchronized based on encountering the signal indicator so as to appropriately switch to a new processing mode.

Abstract: A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status; and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

Abstract: A disclosed method may include (1) publishing, by a writer, a first context that represents a lockless data structure at a first moment in time for access by a set of readers, (2) upon the publication of the first context, directing at least one of the readers to access an object stored in shared memory via the first context, (3) publishing, by the writer, a second context that represents the lockless data structure at a second moment in time for access by the set of readers, and (4) upon the publication of the second context, directing the at least one of the readers to access an additional object stored in the shared memory via the second context. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations on a machine-learning accelerator having multiple tiles. The apparatus includes a processor having a plurality of tiles and scheduling circuitry that is configured to select a respective input activation for each tile of the plurality of tiles from either an activation line for the tile or a delay register for the activation line.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

Abstract: An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Abstract: A unitary solid state drive (SSD) assembly includes a non-volatile memory (NVM), and a processor communicatively coupled to the NVM. The processor is configured to implement a communication protocol configured for accessing solid state memories over a communication network. The unitary SSD assembly also includes a network interface device communicatively coupled to the processor, and network connector coupled to the network interface device. The network interface device is configured to communicate via a network fabric according to a network communication protocol. The NVM, the processor, and the network interface device are arranged in a unitary assembly.

Abstract: A memory controller capable of controlling a memory device to perform a fine program operation, based on a time elapsing from a foggy program completion time and a position of a page on which a fine program is performed controls the memory device including a plurality of pages. The memory controller includes: a fine program timer for recording a foggy program completion time at which a foggy program completion response corresponding to a foggy program operation is received from the memory device, and outputting dummy program instruction information, based on an elapsing amount of time from the foggy program completion time; and a command controller for outputting a fine program command, based on the dummy program instruction information.