Abstract: Configuration devices in a module. In some embodiments, a radio frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a first switch coupled to a first device and a third line. The radio-frequency module further includes a module coupled to the serial bus and the first switch, the module configured to determine whether first data is detected on a first serial data line, determine whether second data is detected on a second serial data line, adjust a configuration of the first switch when the first data is detected on the first serial data line and the second data is detected on the second serial data line.

Abstract: A mode register data processing module is configured to write, in response to a mode register write enable command, first preset data into a reserved mode register in a mode register; an external data transmission module is configured to write, in response to an enable signal, initial data into a memory array via an internal data transmission module according to the first preset data and a preset encoding rule, and is further configured to read target data from the memory array in response to a read command; and a comparison module is configured to determine whether there is an abnormal data transmission based on a comparison result of the first preset data and the target data, and store the comparison result to a preset position in the mode register.

Abstract: An apparatus and method are provided for managing prefetch transactions. The apparatus has an interconnect for providing communication paths between elements coupled to the interconnect. The elements coupled to the interconnect comprise at least a requester element to initiate transactions, and a plurality of completer elements each of which is arranged to respond to a transaction received by that completer element. Congestion tracking circuitry maintains, in association with the requester element, a congestion indication for each of a plurality of routes through the interconnect used to propagate transactions initiated by that requester element. Each route comprises one or more communication paths, and the route employed to propagate a given transaction is dependent on a target completer element for that transaction.

Abstract: To improve utilization of a systolic array, each row of the array is provided with a number of general purpose row input data buses. Each of the general purpose row input data buses can be operable to transfer either feature map (FMAP) input elements or weight values into the processing elements of the corresponding row of the array. By using such general purpose row input data buses, concurrent matrix multiplications as well as faster background weight loading can be achieved in the array.

Abstract: Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.

Abstract: An information handling system may include a processor, a device communicatively coupled to a processor via a communications link including a cable assembly, and a management controller communicatively coupled to the processor and communicatively coupled to the device and the cable assembly via a sideband interface, and configured to: retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device; retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly; combine the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device and the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly into aggregate signal integrity critical parameters; and perform an action relevant to the co

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A control device, an execution device, a device management method, and a device management system are provided, and are related to the field of network technologies. The control device includes: a network communications interface configured to connect to an execution device through a network, where the execution device is a network communications device; and a processor configured to send a device management protocol packet through the network communications interface, where the device management protocol packet indicates an operation performed on a register in a first chip in the execution device and/or the device management protocol packet indicates that a pin of a second chip in the execution device is set to a status indicated by the device management protocol packet.

Abstract: A computer-implemented method may include (1) maintaining (a) a filter matrix in a filter cache included in a local memory device (LMD) included in a hardware accelerator, and (b) a plurality of activation matrices corresponding to different rows of an activation volume in an activation cache included in the LMD, (2) for each activation matrix, directing a matrix multiplication unit (MMU) included in the hardware accelerator to execute a matrix multiplication operation (MMU) using the filter matrix and the activation matrix, (3) loading an additional filter matrix into the filter cache, and (4) directing the MMU to execute a plurality of additional MMOs, each additional MMO using one filter matrix included in the filter cache and one activation matrix included in the activation cache, such that the MMU reuses the filter matrix for at least one additional MMO and uses the additional filter matrix for a different additional MMO.

Abstract: Storage systems are disclosed. For instance, a storage system comprises a first storage device of a first type and a second storage device of a second type, and the first storage device has a higher access velocity than the second storage device. A threshold indicating a volume limit of data stored in the first storage device can be determined. Data, which is specified by a write request for writing data to the storage system, is written to the first storage device in response to determining the data amount in the first storage device is lower than the threshold. A read request from a client device is processed based on data stored in the first storage device. Consequently, the first storage device with a higher access velocity in the storage system may be utilized as much as possible, so that storage device latency in the storage system is managed more effectively.

Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

Abstract: Reversing deletion of a virtual machine including managing, by a storage system, a repository of virtual machine snapshots on a datastore; receiving, by the storage system, a request to recover a deleted virtual machine from the datastore; accessing, by the storage system, the repository of virtual machine snapshots on the datastore to generate a list of deleted virtual machines associated with virtual machine snapshots in the repository of virtual machine snapshots; receiving, by the storage system, a selection of one of the deleted virtual machines in the list of deleted virtual machines; and recovering, by the storage system, the selected deleted virtual machine using a virtual machine snapshot for the selected deleted virtual machine.

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract: An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing an enabling signal to an output device, where the flash controller and the output device are disposed on a printed circuit board (PCB) and intercoupled through wires in the PCB; reading an opcode of the reliable command corresponding to a flash module from the output device, where the flash module is disposed on the PCB and coupled to the flash controller through circuits in the PCB, and the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode; and stopping issuing the enabling signal to the output device after obtaining the opcode of the reliable command.

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.

Abstract: A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.