Patents Examined by Eric K Ashbahian
  • Patent number: 11807518
    Abstract: The present inventions, in one aspect, are directed to micromachined resonator comprising: a first resonant structure extending along a first axis, wherein the first axis is different from a crystal axis of silicon, a second resonant structure extending along a second axis, wherein the second axis is different from the first axis and the crystal axis of silicon and wherein the first resonant structure is coupled to the second resonant structure, and wherein the first and second resonant structures are comprised of silicon (for example, substantially monocrystalline) and include an impurity dopant (for example, phosphorus) having a concentrations which is greater than 1019 cm-3, and preferably between 1019 cm-3 and 1021 cm-3.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: November 7, 2023
    Assignee: SiTime Corporation
    Inventors: Renata M. Berger, Ginel C. Hill, Paul M. Hagelin, Charles I. Grosjean, Aaron Partridge, Joseph C. Doll, Markus Lutz
  • Patent number: 11805692
    Abstract: Provided is an electroluminescent display panel, including: a first region and a second region. The first region includes a plurality of first pixels each including a plurality of first type subpixels and at least one second type subpixel. The second region includes a plurality of second pixels each including a plurality of first type subpixels. The second type subpixel is configured to be light-transmitting and non-light-transmitting in an image acquisition state and in an image display state, respectively.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 31, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zifeng Wang, Yan Ren, Lei Cao, Junmin Sun
  • Patent number: 11804535
    Abstract: A semiconductor device with improved reliability and a method for fabricating the same are provided. The semiconductor device includes a substrate, a first spacer defining a gate trench on the substrate, and a gate electrode in the gate trench, wherein a height of an upper surface of the gate electrode adjacent to the first spacer increases in a direction away from the first spacer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Chul Park
  • Patent number: 11800766
    Abstract: A transparent display device is disclosed, which may improve transmittance in a non-display area and at the same reduce resistance of power lines. The transparent display device includes a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area. The device includes a plurality of power lines provided in the non-display area over the substrate and extended in parallel in a first direction. The display area includes first non-transmissive areas provided with the plurality of subpixels and a first transmissive area provided between the first non-transmissive areas, the non-display area includes second non-transmissive areas provided with the plurality of power lines and a second transmissive area provided between the second non-transmissive areas.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 24, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: KiSeob Shin, ChangSoo Kim, EuiTae Kim, Soyi Lee
  • Patent number: 11793053
    Abstract: A display device includes a substrate, a thin film transistor, a first electrode, an organic light emitting layer, a second electrode and a black matrix layer which is includes a shielding area and an opening area. The opening area is formed in a position corresponding to an emission area where light is emitted from the organic light emitting layer and the shielding area includes a variable light shielding unit which is adjacent to the opening area and has a light transmittance varying in accordance with a wavelength of incident light and a light shielding unit with a constant light transmittance.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 17, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Youngsub Shin, Keunyoung Kim
  • Patent number: 11785793
    Abstract: A method of manufacturing a flip-chip light emitting diode includes: providing a transparent substrate and a temporary substrate, and bonding the transparent substrate with the temporary substrate; grinding and thinning the transparent substrate; providing a light-emitting epitaxial laminated layer having a first surface and a second surface opposite to each other, and including a first semiconductor layer, an active layer and a second semiconductor layer; forming a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer, and bonding the transparent bonding medium layer with the transparent substrate; defining a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer, and manufacturing a first electrode and a second electrode; and removing the temporary substrate.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 10, 2023
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Wei-ping Xiong, Shu-Fan Yang, Chun-Yi Wu, Chaoyu Wu
  • Patent number: 11765958
    Abstract: A display device includes a substrate; a barrier layer above a first surface of the substrate; a protective film below a second surface of the substrate opposite the first surface; an adhesive member between the substrate and the protective film; and an optical sensor below a second surface of the protective film opposite a first surface of the protective film that faces the second surface of the substrate.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hirotsugu Kishimoto
  • Patent number: 11744129
    Abstract: The present invention provides a pixel arrangement structure, a display panel and a display apparatus, each of the plurality of pixel units in the pixel arrangement structure comprises blue sub-pixels, red sub-pixels, and green sub-pixels; the blue sub-pixels, the red sub-pixels, and the green sub-pixels form a center-symmetric pattern, a total area of the blue sub-pixels is greater than a total area of the red sub-pixels, and the total area of the red sub-pixels is greater than a total area of the green sub-pixels, so that there is no need to share sub-pixels with adjacent pixel units, thereby improving the display resolution, and the phenomena of color fringing and edge jagged can be avoided.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 29, 2023
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Kun Wang
  • Patent number: 11735616
    Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die, a memory die, and a sensor die. The logic die includes a front surface. The memory die includes a front surface positioned on the front surface of the logic die, and a back surface opposite to the front surface of the memory die. The sensor die includes a front surface positioned on the back surface of the memory die, a back surface opposite to the front surface of the sensor die, a sensor unit located at the back surface of the sensor die, a color filter positioned on the back surface of the sensor die, and a micro-lens positioned on the color filter.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 22, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Tsung Wu
  • Patent number: 11665950
    Abstract: An object of the present invention is to provide a display device capable of achieving both an effect of preventing reflection of external light and improvement in utilization efficiency of light emitted from a light emitting element. An electroluminescent display device includes a substrate having a plurality of light emitting elements using electroluminescence, a ?/4 wavelength plate, and a polarizing plate including a patterned polarizing layer in this order, in which the patterned polarizing layer has a region A having a polarization degree of less than 80% and a region B having a polarization degree of 80% or more, and further, a position of the region A of the patterned polarizing layer corresponds to a position of the light emitting element of the electroluminescent substrate.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 30, 2023
    Assignee: FUJIFILM Corporation
    Inventor: Takashi Yonemoto
  • Patent number: 11664416
    Abstract: A semiconductor device includes a semiconductor body having a first surface. A first trench extends in a vertical direction into the semiconductor body. The semiconductor device also includes a first interlayer in the first trench and a first dopant source in the first trench. The first interlayer is arranged between the first dopant source and the semiconductor body, and the first dopant source includes a first dopant species. The semiconductor device also includes a semiconductor area doped with the first dopant species and which completely surrounds the first trench at least at a depth in the semiconductor body and adjoins the first trench.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 30, 2023
    Assignee: Infineon Technologies AG
    Inventor: Markus Zundel
  • Patent number: 11653548
    Abstract: A display panel includes a sub-pixel array and a plurality of photosensitive units. The sub-pixel array includes as first sub-pixel, a second sub-pixel and a third sub-pixel that are capable of emitting light of different colors. The plurality of photosensitive units are disposed under a light-emitting surface of the sub-pixel array. Each of the plurality of photosensitive units includes a photosensitive device, and the photosensitive device includes a photosensitive layer; and an orthographic projection of the photosensitive layer in the photosensitive device on a panel surface of the display panel has overlapping regions with orthographic projections of the first sub-pixel, the second sub-pixel and the third sub-pixel on the panel surface of the display panel.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: May 16, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuzhen Guo, Xiaochuan Chen, Lei Wang, Haisheng Wang, Yingming Liu, Lijun Zhao, Changfeng Li
  • Patent number: 11641770
    Abstract: A display panel is provided. At least two of each of first pixels, each of second pixels, and each of third pixels of the display panel are alternately arranged. A shape of each of first pixels includes an ellipse or a circle. A shape of an edge of each of the second pixels or each of the third pixels corresponds to a concave arc. A sum of a radius of curvature of an edge of each of the first pixels and a width of a predetermined gap is equal to a radius of curvature of the concave arc corresponding to the edge of one of each of the second pixels and each of the third pixels. An aperture ratio of a pixel is effectively increased.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 2, 2023
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yong Zhao, Liang Sun, Shoucheng Wang, Yaojen Chang
  • Patent number: 11616167
    Abstract: A nitride semiconductor light-emitting element includes an n-type cladding layer including n-type AlGaN, and a multiple quantum well layer including a barrier layer that includes AlGaN and is located on the n-type cladding layer side, wherein the nitride semiconductor light-emitting element further comprises a trigger layer that is located between the n-type cladding layer and the barrier layer and comprises Si, wherein a plural V-pits starting from dislocations in the n-type cladding layer and ending in the multiple quantum well are formed in the n-type cladding layer and the multiple quantum well layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 28, 2023
    Assignee: Nikkiso Co., Ltd.
    Inventors: Cyril Pernot, Yusuke Matsukura, Yuta Furusawa, Mitsugu Wada
  • Patent number: 11616144
    Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunguk Jang, Sujin Jung, Jinyeong Joe, Jeongho Yoo, Seung Hun Lee, Jongryeol Yoo
  • Patent number: 11611005
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Patent number: 11600698
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Patent number: 11594552
    Abstract: Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: February 28, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Bo Xu, Ping Yan, Chuan Yang, Jing Gao, Zongliang Huo, Lu Zhang
  • Patent number: 11587940
    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, first to fourth stack structures spaced apart in a first direction on the second substrate, first and second support connectors between the second and third stack structures, third and fourth support connectors between the third and fourth stack structures, and a through dielectric pattern penetrating the first stack structure and the second substrate. A first distance between the first and second support connectors is different from a second distance between the third and fourth support connectors.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 21, 2023
    Inventors: Seokcheon Baek, Geunwon Lim, Jaehoon Shin, Myungkeun Lee
  • Patent number: 11574979
    Abstract: An opening, which is provided on the inner side of a first pixel electrode, which is a first electrode formed in a display region, is larger than an opening, which is provided on the inner side of a second pixel electrode, which is the first electrode formed in a dummy display region. Further, a light-emitting layer (a first light-emitting layer) formed in the display region has the same shape and the same size as a light-emitting layer (a second light-emitting layer) formed in the dummy display region.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 7, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Abe, Takeshi Yaneda