Abstract: A pixel arrangement structure, a display substrate and a mask group are disclosed. The pixel arrangement structure includes a plurality of pixel groups, each of the plurality of pixel groups includes one red sub-pixel, two green sub-pixels and one blue sub-pixel; the red sub-pixel and the blue sub-pixel are arranged along a first direction; the two green sub-pixels are arranged along a second direction. Four vertexes included in the red sub-pixel are located in a first virtual rhombus and are substantially coincident with four vertexes of the first virtual rhombus, respectively; four vertexes included in the blue sub-pixel are located in a second virtual rhombus and are substantially coincident with four vertexes of the second virtual rhombus, respectively; at least one of the red or the blue sub-pixel has a shape of a corresponding virtual rhombus with each side of the virtual rhombus being an inwardly concaved side.

Abstract: A pixel arrangement structure of display panel and a display apparatus, which are used to solve the technical problem of low pixel aperture ratio of an organic light emitting diode display panel. Herein, a pixel arrangement structure of display panel includes: a plurality of sub-pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel; where the first sub-pixel, the second sub-pixel, and the third sub-pixel have a polygonal structure with different numbers of sides, and distances between any adjacent two of the plurality of sub-pixels are equal.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: A display panel includes at least two pixel repeating units arranged in an array. Each of the pixel repeating units at least includes a first pixel, a second pixel, and a third pixel. A shape of the first pixel includes a convex arc, and each of shapes of the second pixel and the third pixel includes a convex arc and a concave arc. Shapes of edges of two of the first pixel, the second pixel, and the third pixel are complementary in at least one of a first direction, a second direction, a third direction, and a fourth direction, the first direction is perpendicular to the second direction, the third direction is a direction having an angle of less than 90 degrees with the first direction, and the fourth direction is perpendicular to the third direction.

Abstract: A display panel, a method for fabricating a display panel and a display apparatus are provided. The display panel includes a substrate; a plurality of discrete first electrodes, a pixel define layer, a metal connection layer disposed on a side of the pixel define layer facing away from the substrate, wherein an orthographic projection of the metal connection layer on the substrate at least surrounds half of each opening of the plurality of openings; an organic light-emitting layer, and at least one second electrode, disposed on a side of the organic light-emitting layer and the pixel define layer facing away from the substrate. An orthographic projection of the at least one second electrode on the substrate covers an orthographic projection of the pixel define layer and the plurality of first electrodes on the substrate and the at least one second electrode is electrically connected to the metal connection layer.

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

Abstract: The present disclosure provides a light emitting device and a method for manufacturing the same, and a display device. The light emitting device includes a plurality of light emitting units including a red light emitting unit, a green light emitting unit, and a blue light emitting unit, each light emitting unit including a micro-cavity structure. The light emitting device includes an anode structure, a cathode and a functional layer therebetween. The functional layer includes a light emitting layer including a red light emitting layer at least partially located in the red light emitting unit, an orthographic projection of the red light emitting layer on the backplane not overlapping with that of the blue light emitting unit on the backplane; a green light emitting layer at least partially located in the green light emitting unit; and a blue light emitting layer at least partially located in the blue light emitting unit.

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Abstract: A display substrate, a display panel and a display device are provided. The display substrate has a plurality of sub-pixel regions and a plurality of inter-sub-pixel regions between the plurality of sub-pixel regions. The display substrate includes a plurality of sub-pixels located in the plurality of sub-pixel regions and at least one separation pillar, and at least one sub-pixel region is provided with at least one separation pillar therein.

Abstract: A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

Abstract: Provided are a display panel and a display device. The display panel includes pixel unit groups arranged in a matrix, where a row direction of the matrix is a first direction; in a same pixel unit group, geometric centers of two first sub-pixels and geometric centers of two second sub-pixels form a first virtual parallelogram, where the first virtual parallelogram includes two first sides extending along the first direction and two second sides extending along a second direction, and the second direction intersects and is not perpendicular to the first direction; a geometric center of one third sub-pixel is located inside the first virtual parallelogram, the other three third sub-pixels are located outside the first virtual parallelogram, and geometric centers of the four third sub-pixels form a second virtual parallelogram, where the second virtual parallelogram includes two third sides extending along the first direction, and two fourth sides extending along the second direction.

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

Abstract: A display device according to an embodiment of the inventive concept provides includes a substrate, a green light emitting element group and a blue light emitting element group, which are repeatedly arranged in a first direction parallel to a top surface of the substrate, and a red conversion pattern on the green light emitting element group and the blue light emitting element group. Here, the red conversion pattern overlaps a portion of the green light emitting element group and a portion of the blue light emitting element group in a second direction perpendicular to the top surface of the substrate.

Abstract: The present disclosure relates to a glass interposer module, an imaging device, and an electronic apparatus capable of reducing occurrence of distortion caused by thermal expansion during manufacture. A light transmissive member is charged between a glass interposer and a CMOS image sensor (CIS). Since rigidity of the glass interposer can be enhanced by this configuration, it is possible to suppress deflection of the CIS and also reduce influence of distortion given to a gyro sensor and the like which are equipped on the glass interposer, and therefore, erroneous detection of a gyro signal can be reduced. The present disclosure can be applied to a glass interposer module.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a display region including a first display region and a photo-sensitive element disposing region. The photo-sensitive element disposing region includes a light-transmitting region and a light-blocking region. The display panel further includes a base substrate and a plurality of pixel units on the base substrate. The light-blocking region includes at least one pixel unit which includes a plurality of sub-pixels. Along a direction perpendicular to a plane of the base substrate, the light-blocking region at least includes a first convex arced edge.

Abstract: An avalanche photodiode (APD) sensor includes a photoelectric conversion region disposed in a substrate and that converts light incident to a first side of the substrate into electric charge, and a cathode region disposed at a second side of the substrate. The second side is opposite the first side. The APD sensor includes an anode region disposed at the second side of the substrate, a first region of a first conductivity type disposed in the substrate, and a second region of a second conductivity type disposed in the substrate. The second conductivity type is different than the first conductivity type. In a cross-sectional view, the first region and the second region are between the photoelectric conversion region and the second side of the substrate. In the cross-sectional view, an interface between the first region and the second region has an uneven pattern.

Abstract: A light-emitting device comprising first and second light-emitting elements in a display region, and first and second dummy elements in a dummy region is provided. Each of the light-emitting elements, and the dummy elements includes a reflector arranged, a first electrode arranged above the reflector, a light-emitting layer arranged above the first electrode, and a second electrode arranged above the light-emitting layer. A difference between a distance from the reflector to the light-emitting layer in the first light-emitting element and a distance from the reflector to the light-emitting layer in the second light-emitting element is larger than a difference between a distance from the reflector to the light-emitting layer in the first dummy element and a distance from the reflector to the light-emitting layer in the second dummy element.

Abstract: Group III nitride light emitting diode (LED) structures with improved electrical performance are disclosed. A Group III nitride LED structure includes one or more n-type layers, one or more p-type layers, and an active region that includes a plurality of sequentially arranged barrier-well units. In certain embodiments, doping profiles of barrier layers of the barrier-well units are configured such that a doping concentration in some barrier-well units is different than a doping concentration in other barrier-well units. In certain embodiments, a doping profile of a particular barrier layer is non-uniform. In addition to active region configurations, the doping profiles and sequence of the n-type layers and p-type layers are configured to provide Group III nitride structures with higher efficiency, lower forward voltages, and improved forward voltage performance at elevated currents and temperatures.