Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a display region and a non-display region located at a periphery of the display region. The display region includes a plurality of pixel structures, and an outgoing line of each of the pixel structures is overlapped with and connected to a connection line. The connection line receives a signal provided by a signal supply circuit. An area of a contact interface between at least part of the connection line and the outgoing line is larger than an area of an orthographic projection of the contact interface on a plane where the array substrate is located.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

Abstract: The present invention provides an organic light-emitting diode (OLED) pixel structure, including: a plurality of pixel groups having predetermined shapes that constitute a pixel layer, one of the pixel groups having predetermined shapes including at least two pixels of R, G, and B pixels and no common sub-pixel, each of the pixels including three sub-pixels having different areas, and areas of same sub-pixels in different pixels in one of the pixel groups having predetermined shapes are equal.

Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Abstract: A display panel and a display device including the display panel are provided. The display panel includes first pixel units arranged in a first display area and second pixel units arranged in a second display area, a density of the first pixel units in the first display area is smaller than a density of the second pixel units in the second display area, each of the first pixel units includes a first anode comprising a first reflective metal layer and a first transparent conductive layer, the first reflective metal layer and the first transparent conductive layer are stacked on each other, and an area of the first reflective metal layer is smaller than an area of the first transparent conductive layer.

Abstract: A display panel includes a pixel arrangement structure. The pixel arrangement structure includes a plurality of first pixel rows and a plurality of second pixel rows arranged alternately. Each of the first pixel rows comprises a plurality of first pixels arranged at intervals, and each of the second pixel rows comprises a plurality of second pixels and a plurality of third pixels arranged alternately and at intervals. A shape of the first pixel comprises a shape formed by an arc. Each of the second pixel and the third pixel comprises a plurality of concave arcs and a plurality of convex arcs, the plurality of concave arcs and the plurality of convex arcs of the second pixel are alternately connected and form a closed figure, and the plurality of concave arcs and the plurality of convex arcs of the third pixel are alternately connected and form a closed figure.

Abstract: A semiconductor device package includes a resin unit having a first through hole and a second through hole, a conductive body disposed on the resin unit and having a cavity that is concave in a first direction from a top surface of the conductive body toward a bottom surface thereof, and a light-emitting device disposed in the cavity, wherein the conductive body includes a first protrusion and a second protrusion, which protrude in the first direction from the bottom surface of the conductive body, and the first protrusion is disposed inside the first through hole, the second protrusion is disposed inside the second through hole, and a top surface of the resin unit is in contact with the bottom surface of the conductive body.

Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

Abstract: Light-emitting diodes (LEDs), LED arrays, and related devices are disclosed. An LED device includes a first LED chip and a second LED chip mounted on a submount with a light-altering material in between. The light-altering material may include at least one of a light-reflective material and/or a light-absorbing material. Individual wavelength conversion elements may be arranged on each of the first and second LED chips. The light-altering material may improve the contrast between the first and second LED chips as well as between the individual wavelength conversion elements. LED devices may include submounts in modular configurations where LED chips may be mounted on adjacent submounts to form an LED array. Each LED chip of the LED array may be laterally separated from at least one other LED chip by a same distance and a light-altering material may be arranged around the LED array.

Abstract: A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a widt

Abstract: Provided are a display panel and display device. The display panel includes a first display region and a second display region adjacent to the first display region. The second display region includes multiple first light-emitting elements, the first light-emitting element includes a first electrode, a second electrode and a light-emitting layer located between the first electrode and the second electrode, a direction from the light-emitting layer to the first electrode is a light exit direction of the display panel, the second electrode includes a photochromic layer, the photochromic layer includes a photochromic material, the second electrode includes a first state and a second state, and a light transmittance of the second electrode in the first state is greater than a light transmittance of the second electrode in the second state.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Abstract: Light-emitting diodes (LEDs), LED arrays, and related devices are disclosed. An LED device includes a first LED chip and a second LED chip mounted on a submount with a light-altering material in between. The light-altering material may include at least one of a light-reflective material and/or a light-absorbing material. Individual wavelength conversion elements may be arranged on each of the first and second LED chips. The light-altering material may improve the contrast between the first and second LED chips as well as between the individual wavelength conversion elements. The light-altering material may include at least one of nanoparticles, nanowires, mesowires, or combinations thereof. LED devices may include submounts in modular configurations where LED chips may be mounted on adjacent submounts to form an LED array.

Abstract: An image sensor assembly and a method for assembling. The assembly includes: a ceramic package; at least one wall raised from the ceramic package, one of the walls for dividing a first surface region and a second surface region of the ceramic package; a frame supported by the ceramic package; a first set of fiducial markers and a second set of fiducial markers visible on the frame; a first die for placement onto the first surface region, the first die including an image sensor and respective fiducial markers for alignment with the first set of fiducial markers; a second die for placement onto the second surface region, the second die including an image sensor and respective fiducial markers for alignment with the second set of fiducial markers; and at least one optical filter each associated with one of the dice and supported by at least one of the walls.

Abstract: Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of conductor/dielectric layer pairs, a plurality of memory strings each extending vertically through the memory stack, a slit contact disposed laterally between the plurality of memory strings, and a composite spacer disposed laterally between the slit contact and at least one of the memory strings. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film disposed laterally between the first silicon oxide film and the second silicon oxide film.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.

Abstract: A pixel arrangement structure, a display substrate and a display device. The pixel arrangement structure includes: a plurality of first sub-pixels and a plurality of sub-pixel groups arranged in an array, wherein the plurality of first sub-pixels and the plurality of sub-pixel groups are alternately arranged along a first direction to form pixel rows, and are alternately arranged along a second direction intersected with the first direction to form pixel columns; each of the plurality of sub-pixel groups includes a second sub-pixel, a third sub-pixel and another second sub-pixel sequentially arranged along the first direction; in the same pixel row, a ratio of a distance between the geometric centers of each second sub-pixel and the adjacent third sub-pixel to a distance between the geometric centers of each first sub-pixel and the third sub-pixel in the adjacent sub-pixel group is greater than or equal to ¼ and less than ½.