Abstract: Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction.

Abstract: In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.

Abstract: A method of forming one or more three-dimensional objects for an optoelectronic lighting device including a carrier with an optoelectronic semiconductor component includes providing a carrier of an optoelectronic lighting device, wherein an optoelectronic semiconductor component is arranged on the carrier, and a construction region partly delimited by the carrier is defined, the optoelectronic semiconductor component facing the construction region, introducing a polymerizable liquid into the construction region, and exposing the construction region to form one or more solid polymers from the polymerizable liquid in a curing zone included by the construction region, and one or more three-dimensional objects from the one or more solid polymers in the curing zone, wherein an ineffective region is formed during the process of exposing the construction region, polymerization being inhibited in the ineffective region, and the curing zone is arranged between the carrier and the ineffective region.

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Abstract: Provided are an encapsulation film, an organic electronic device (OED) comprising the same, and a method of manufacturing the organic electronic device. When the organic electronic device is encapsulated using the encapsulation film, an excellent moisture barrier property may be realized, and as reflection or scattering of light is prevented by absorbing and blocking internal or external light, external defects of the organic electronic device may be prevented.

Abstract: The present embodiments provide a flexible, lightweight and highly efficient photoelectric conversion device and further provide a manufacturing method thereof. The photoelectric conversion device according to the embodiment comprises a laminate structure of a substrate, an ITO electrode, a photoelectric conversion layer and a counter electrode. When subjected to surface X-ray diffraction analysis, the ITO electrode shows an X-ray diffraction profile characterized in that the peak at a diffraction peak position in the range of 2?=30.6±0.5° has a half-width of 1.0° or less. The ITO electrode in the device can be formed by forming an amorphous-phase ITO film on the substrate and then by subjecting the film to annealing treatment at a temperature of 200° or less.

Abstract: An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.

Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about ?100° C. to about 100° C.

Abstract: The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

Abstract: A display device includes a substrate including a display area, the display area including a plurality of pixels and a non-display area positioned around the display area, and the non-display area including a pad portion. A bending portion having a curvature is located in the non-display area and a first protection layer is at one surface of the bending portion having the curvature in the non-display area. A second protection layer entirely covers one surface of the bending portion having the curvature in the non-display area, the second protection layer being positioned outermost of the substrate and the first protection layer based on a center of a curvature radius of the bending portion. The second protection layer is thinner than the first protection layer. The second protection layer has a wider area than the first protection layer.

Abstract: Disclosed according to one embodiment is a lighting device comprising: a light emitting device having a light emitting chip; and an optical plate corresponding to the light emitting chip, wherein the optical plate comprises: a phosphor layer; a transparent film on the upside and/or downside of the phosphor layer; and a support surrounding the outside of the phosphor layer.

Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.

Abstract: A display device includes a first substrate defining a top surface thereof, a bottom surface thereof facing the top surface, and side surfaces thereof connecting the top and bottom surfaces to each other. The side surfaces included: a first side surface defined by: a first patterned surface including a first pattern of which a length thereof extends in a diagonal direction in a plan view of the first patterned surface, and a second patterned surface which extends obliquely from an upper end of the first patterned surface, the second patterned surface including a second pattern of which a length thereof extends in a perpendicular direction from the upper end of the first patterned surface in a plan view of the second patterned surface.

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Abstract: The invention belongs to the technical field of semiconductor material preparation, and in particular provides a preparation method of tin doped n-type gallium oxide. To pre-deposit the appropriate tin doping source on gallium oxide materials in proper ways. The gallium oxide material is then placed in a high temperature tube in an appropriate manner. Then the tin atoms can be controlled to diffuse into the gallium oxide material by heat treatment at a certain temperature for a period of time. Then the tin atoms can be activated as an effective donor to realize the n-type doping of the gallium oxide material. In this invention, the doping can be realized after the preparation of the gallium oxide material is completed, and the necessary equipment and process are simple, and the doping controllability is high.

Abstract: A display device includes: a substrate including a display area for displaying an image and a peripheral area positioned adjacent to the display area; a plurality of normal pixels disposed within the display area on the substrate, where each normal pixel includes a first transmissive area and a pixel area disposed adjacent the first transmissive area; and a dummy pixel disposed within the display area on the substrate, adjacent to a curved section of the peripheral area, and disposed between the peripheral area and the plurality of pixels. The dummy pixel includes: a second transmissive area; and a wire area disposed adjacent the second transmissive area.

Abstract: A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p?-doped epitaxial first layer disposed on the drift zone, a heavily n-doped second layer disposed on the first layer, and a terminal formed by p+ implantation, the first layer being in electrical contact with the terminal and being disposed laterally between the terminal and a trench, the trench being formed in the drift zone, in the first layer, and in the second layer. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.