Patents Examined by Ermias T Woldegeorgis
  • Patent number: 10828725
    Abstract: A method of inspection of a laser-irradiated nickel film is disclosed. The method may include: reducing a surface of the laser-irradiated nickel film under a reducing gas atmosphere; heating the surface of the nickel film at 250 degrees Celsius or higher under a nitrogen atmosphere after the reducing; measuring a color of the surface of the nickel film after the heating; and assessing a condition of the surface of the nickel film based on a result of the color measuring.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 10, 2020
    Assignee: DENSO CORPORATION
    Inventors: Sachiko Nakajima, Atsushi Fukunishi
  • Patent number: 10818700
    Abstract: The disclosure discloses an array substrate, a liquid crystal display panel, and a display device, and the array substrate includes: a base substrate; a plurality of pixel units with pixel electrodes on the base substrate; where each of at least a part of the plurality of pixel units is provided with at least one recess, and a pixel electrode in each of the at least a part of the plurality of pixel units covers the at least one recess; where an orthographic projection of an opening of each recess onto the base substrate overlaps with an orthographic projection of a bottom thereof onto the base substrate, and an area of the orthographic projection of the opening of the recess onto the base substrate is greater than an area of the orthographic projection of the bottom thereof onto the base substrate.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 27, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yongda Ma, Xinyin Wu, Yong Qiao
  • Patent number: 10818712
    Abstract: Provided is a solid-state image pickup device and a method of manufacture, and an electronic device capable of suppressing occurrence of a transmission wavelength shift with a simpler design. The solid-state image pickup device includes a multilayer film filter having a laminated structure in which a transmission wavelength adjustment layer is sandwiched between a first multilayer film layer and a second multilayer film layer. The transmission wavelength adjustment layer is formed such that at least two types of dielectrics having different refractive indexes mixedly exist, and an effective refractive index is determined according to a ratio of the mixture. The effective refractive index of the transmission wavelength adjustment layer gradually increases from a chip central portion in which an incident angle of light emitted onto the multilayer film filter is small toward a chip end portion in which the incident angle of light is large.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 27, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuji Yamaguchi, Atsushi Toda
  • Patent number: 10804383
    Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes disposed on a side face of a first insulating support and on a side face of a second insulating support, respectively; an island disposed between the first and second S/D electrodes and extending into an area between the first and second insulating supports. In some embodiments, a SET device may include: first and second S/D electrodes disposed on a substrate; an island disposed in an area between the first and second S/D electrodes; first and second portions of dielectric disposed between the island and the first and second S/D electrodes, respectively; and a third portion of dielectric disposed between the substrate and the island.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventor: Hubert C. George
  • Patent number: 10793427
    Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 6, 2020
    Assignee: KIONIX, INC.
    Inventors: Martin Heller, Toma Fujita
  • Patent number: 10790281
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys
  • Patent number: 10784152
    Abstract: A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 22, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Heng Liu
  • Patent number: 10784419
    Abstract: A light emitting device includes a light emitting element; a sealing resin covering the light emitting element; and a light diffusing material contained in the sealing resin. When a difference in refractive index at 10° C. between the sealing resin and the light diffusing material is ?n1 and a difference in refractive index at 50° C. between the sealing resin and the light diffusing material is ?n2, a ratio of ?n2 to ?n1 is in a range of 95% to 105%.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 22, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Motokazu Yamada, Tomonori Ozaki, Shinsaku Ikuta, Yuichi Yamada
  • Patent number: 10777499
    Abstract: A conductive thin-film thinner than the undersurface electrode is provided outside the undersurface electrode on the undersurface of the ceramic substrate and connected to the undersurface electrode. A length from an outer circumferential part of the undersurface electrode to an outer circumferential pert of the ceramic substrate is equal to a length from an outer circumferential part of the top surface electrode to an outer circumferential part of the ceramic substrate. A thickness of the conductive thin-film is half or less than a thickness of the ceramic substrate.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuo Tanaka
  • Patent number: 10777704
    Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 15, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Koji Matsumoto, Toshiaki Ono, Hiroshi Amano, Yoshio Honda
  • Patent number: 10770622
    Abstract: One embodiment of a light-emitting element comprises: a substrate; a first-conductive type semiconductor layer disposed on the substrate and including at least one pit; a superlattice layer disposed on the first-conductive type semiconductor layer and including at least one pit; an active layer disposed on the superlattice layer and including at least one pit; an electron blocking layer disposed on the active layer and including at least one pit; a pit layer disposed on the electron blocking layer and including at least one pit; and a second-conductive type semiconductor layer disposed on the pit layer, wherein the pit layer can be doped with Mg at at least a portion thereof.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 8, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Young Hun Han
  • Patent number: 10766767
    Abstract: A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 8, 2020
    Assignee: KIONIX, INC.
    Inventors: Martin Heller, Toma Fujita
  • Patent number: 10763279
    Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masaki Tsuji, Yoshiaki Fukuzumi
  • Patent number: 10745572
    Abstract: An optical filter includes an absorption layer containing a near-infrared absorbing dye with an absorption characteristic in dichloromethane satisfying (i-1) to (i-3). (i-1) In an absorption spectrum of a wavelength of 400 to 800 nm, there is a maximum absorption wavelength ?max in 670 to 730 nm. (i-2) Between a maximum absorption coefficient ?A of light with a wavelength of 430 to 550 nm and a maximum absorption coefficient ?B of light with a wavelength of 670 to 730 nm, the following relational expression: ?B/?A?65 is established. (i-3) In a spectral transmittance curve, the difference between a wavelength ?80 with which the transmittance becomes 80% on a shorter wavelength side than the maximum absorption wavelength with the transmittance at the maximum absorption wavelength ?max set to 10% and the maximum absorption wavelength ?max is 65 nm or less.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 18, 2020
    Assignee: AGC Inc.
    Inventors: Kazuhiko Shiono, Keigo Matsuura, Hiroki Hotaka
  • Patent number: 10748835
    Abstract: A cooling device includes an aluminum heat sink and at least one nickel sheet segment. The nickel sheet segment is connected to the aluminum heat sink by a solder layer. The cooling device includes a securing surface for securing and for heat absorption. The securing surface being formed by that side of the nickel sheet segment which faces away from aluminum heat sink. The aluminum heat sink is formed from a plurality of aluminum sheets which are stacked one above another and are connected to one another. At least one aluminum sheet includes cutouts which form a cooling channel covered by at least one of the aluminum sheets. Furthermore, a method for producing a cooling device and also a power circuit comprising a heat sink as described here are presented.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 18, 2020
    Assignee: CPT Group GmbH
    Inventors: Arnoud Smit, Thomas Schmid, Lars Keller, Soeren Rittstieg
  • Patent number: 10748730
    Abstract: A photocathode utilizes an field emitter array (FEA) integrally formed on a silicon substrate to enhance photoelectron emissions, and a thin boron layer disposed directly on the output surface of the FEA to prevent oxidation. The field emitters are formed by protrusions having various shapes (e.g., pyramids or rounded whiskers) disposed in a two-dimensional periodic pattern, and may be configured to operate in a reverse bias mode. An optional gate layer is provided to control emission currents. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the second boron layer. An optional external potential is generated between the opposing illuminated and output surfaces. An optional combination of n-type silicon field emitter and p-i-n photodiode film is formed by a special doping scheme and by applying an external potential. The photocathode forms part of sensor and inspection systems.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 18, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Yung-Ho Alex Chuang, John Fielden, Yinying Xiao-Li, Xuefeng Liu
  • Patent number: 10741444
    Abstract: In a method according to an exemplary embodiment, a substrate is prepared in a chamber. A patterned resist mask has been formed on a first region of the substrate. A surface of the substrate in a second region is exposed. A film is formed on the substrate in the chamber by sputtering. The film is formed on the substrate in a manner that particles emitted obliquely downward from a target are caused to be incident onto the substrate.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 11, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hidetami Yaegashi
  • Patent number: 10734293
    Abstract: Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 4, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventor: Jeffrey Drue David
  • Patent number: 10727304
    Abstract: In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Kitamura
  • Patent number: 10727382
    Abstract: A method of forming one or more three-dimensional objects for an optoelectronic lighting device including a carrier with an optoelectronic semiconductor component includes providing a carrier of an optoelectronic lighting device, wherein an optoelectronic semiconductor component is arranged on the carrier, and a construction region partly delimited by the carrier is defined, the optoelectronic semiconductor component facing the construction region, introducing a polymerizable liquid into the construction region, and exposing the construction region to form one or more solid polymers from the polymerizable liquid in a curing zone included by the construction region, and one or more three-dimensional objects from the one or more solid polymers in the curing zone, wherein an ineffective region is formed during the process of exposing the construction region, polymerization being inhibited in the ineffective region, and the curing zone is arranged between the carrier and the ineffective region.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 28, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Nikolaus Gmeinwieser