Abstract: A power module that can realize insulation performance by suppressing the occurrence of bubbles in silicone gel and the detachment between the silicone gel and an insulating substrate during high temperature, during low temperature and during low atmospheric pressure, to thereby suppress degradation of insulation performance. The power module includes: an insulating substrate having a front surface on which a power semiconductor element is mounted; a base plate joined to a back surface of the insulating substrate; a case fixed to the base plate and surrounding the insulating substrate; a cover fixed to the case and forming a sealed region; and a silicone gel serving as a filling member filling the entire sealed region and having internal stress maintained at compressive stress.

Abstract: A method of processing a wafer includes a cutting step of cutting the face side of the wafer with a cutting blade to form grooves therein along projected dicing lines, a first inspecting step of capturing an image of the grooves formed in the cutting step and inspecting a state of a chip in the captured image of the grooves, a protecting member sticking step of sticking a protective member to the face side of the wafer, a grinding step of holding the protective member side of the wafer on a chuck table and grinding a reverse side of the wafer to thin the wafer to a finished thickness, thereby dividing the wafer into device chips, a second inspecting step of capturing an image of the grooves exposed on the reverse side of the wafer and inspecting a state of a chip in the captured image of the grooves.

Abstract: An array substrate, a repair method of the array substrate, a display panel and a display device are provided. The array substrate includes a base substrate, and a common electrode layer, a common electrode line mesh, a first metal layer and a second metal layer which are on the base substrate, and the common electrode line mesh is electrically connected with the common electrode layer. The first metal layer includes a first signal line extending along a first direction; the second metal layer includes a second signal line extending along a second direction and a plurality of repair connection portions; and each repair connection portion has a first overlap portion overlapping the first signal line and a second overlap portion overlapping the common electrode line mesh.

Abstract: In a method according to embodiments of the invention, for a predetermined amount of light produced by a light emitting diode and converted by a phosphor layer comprising a host material and a dopant, and for a predetermined maximum reduction in efficiency of the phosphor at increasing excitation density, a maximum dopant concentration of the phosphor layer is selected.

Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.

Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.

Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate including a first region, a second region separated from the first region, and a bending region positioned between the first and second regions. The bending region is configured to be bent so as to have a plurality of different curvatures depending on degrees of bending of the flexible substrate. The display device also includes a first display unit positioned in the first region, a second display unit separated from the first display unit and positioned in the second region and an encapsulation layer positioned over the flexible substrate with the first and second display units interposed therebetween. The encapsulation layer directly contacts the bending region of the flexible substrate.

Abstract: Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.

Abstract: Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired.

Abstract: Barrier infrared detectors having structures configured to enhance the quantum efficiency, and methods of their manufacture are provided. In particular, device structures for constructing high-performance barrier infrared detectors using novel combinations of p-type and n-type absorber regions and contact regions are provided. The infrared detectors generally incorporate a “p+Bpnn+” structure. The detectors generally comprise, in sequence, a highly p-doped contact layer “p+”, an electron unipolar barrier “B”, a p-type absorber section “p”, and n-type absorber section “n”, and a highly n-doped contact layer “n+”.

Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

Abstract: A method is provided for creating an interdigitated pattern for a back-contacted solar cell, including deposition of a first passivation layer stack including a-Si of a first doping type, patterning the first passivation layer stack by using a first dry etching process to create one or more regions including the a-Si of the first doping type and one or more exposed regions of the surface, cleaning the one or more exposed regions of the surface from contaminants remaining from the first dry etching process, and depositing a second passivation layer stack including a-Si of a second doping type different from the first doping type to create the interdigitated pattern together with the patterned first passivation layer stack. The cleaning may include depositing a sacrificial layer at least on the exposed regions of the surface, and removing the sacrificial layer by a second dry etching process, at a temperature not exceeding 250° C.

Abstract: A film-forming composition having favorable effects such as curability and embeddability and resist underlayer film for use in lithography process for semiconductor devices. The film-forming composition including, as silane, hydrolyzable silane, hydrolysis product thereof, or hydrolysis-condensation product thereof, wherein hydrolyzable silane includes hydrolyzable silane of Formula (1): R1aR2bSi(R3)4?(a+b)??Formula (1) in Formula (1), R1 is organic group of Formula (2) and is bonded to silicon atom through Si—C bond: The film-forming composition, wherein the hydrolyzable silane is combination of hydrolyzable silane of Formula (1) with another hydrolyzable silane, wherein other hydrolyzable silane is at least one selected from group made of hydrolyzable silane of Formula (3): R7cSi(R8)4?c??Formula (3) and hydrolyzable silane of Formula (4): R9dSi(R10)3?d2Ye??Formula (4) Resist underlayer film, obtained by applying the resist underlayer film-forming composition on semiconductor substrate and baking.

Abstract: An optical package is proposed comprising a carrier, an optoelectronic component, an aspheric lens, and a reflective layer. The carrier comprises electrical interconnections and the optoelectric component is arranged for emitting and/or detecting electromagnetic radiation in a specified wavelength range. Furthermore, the optoelectric component is mounted on the carrier or integrated into the carrier and electrically connected to the electric interconnections. The aspheric lens has an upper surface, a lateral surface, and a bottom surface and the bottom surface is arranged on or near the optoelectric component. The aspheric lens comprises a material which is at least transparent in the specified wavelength range. The reflective layer comprises a reflective material, wherein the reflective layer at least partly covers the lateral surface of the aspheric lens, and wherein the reflective material is at least partly reflective in the specified wavelength range.

Abstract: A substrate on which a processing film made of a directed self-assembly material is formed is placed on a holding plate incorporating a preheating mechanism, and is preheated. A low oxygen atmosphere surrounds the substrate. A preheating temperature is a temperature at which the directed self-assembly material comprised of two types of polymers is phase-separated. By preheating the processing film, the two types of polymers are phase-separated to form a fine pattern. The processing film is irradiated with flashes of light from flash lamps while being preheated. This increases the fluidity of the polymers constituting the processing film to achieve the formation of a fine pattern while suppressing the occurrence of defects.

Abstract: Multi-mode resonator is usually used to design broadband bandpass filters and the cross-shape resonator (CSR) is one of its typical types. The possibility of utilizing cross-shape multi-mode resonators is explored as a signal controller for superconducting qubits that are coplanar to the resonator. The multi-mode qubit-resonator coupling facilitates the design of future quantum information processor.

Abstract: A semiconductor device with a shallow trench isolation structure includes a semiconductor substrate having a first region and a second region, a plurality of fins on the first and second regions, a first isolation region between the first and second regions, the first isolation region having an upper portion doped with ions, and a second isolation region between the fins. The doped upper portion is characterized by a reduced etch rate so that the thickness of the first isolation region is thicker than the second isolation region.