Abstract: Embodiment of the present disclosure provides a system, a computer program product and a method for managing a peripheral component interface express device hotplug by receiving an operation command from a user through a user command interface module; sending, in response to reception of the operation command, the operation command to a hotplug management module via an interface provided by a hotplug interface library; and performing, by the hotplug management module, the operation command by means of at least one of an interface provided by an operating system, a kernel of the operating system, and at least one of a corresponding plurality of hotplug group service modules, in response to receiving the operation command.

Abstract: A method for allocating a resource to multiple requesters is disclosed. In one embodiment, such a method includes maintaining, for a resource, a regular queue and an express queue. The method receives requests to control the resource and determines, for each request, an anticipated amount of time that the request needs to control the resource. In the event the anticipated amount of time for a request is greater than a selected threshold, the method allocates the request to the regular queue. In the event the anticipated amount of time for a request is less than the selected threshold, the method allocates the request to the express queue. The method provides priority to requests allocated to the express queue over requests allocated to the regular queue. A corresponding system and computer program product are also disclosed.

Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.

Abstract: A coupler for an automation system for controlling a process, having a first interface for connection to a field bus for receiving a field bus message with process data of the process, a second interface for connection to a local bus for transmitting a local bus message, and a circuit implemented between the first interface and the second interface. The circuit has a non-clocked logic circuit comprising a number of hardware logic elements. The non-clocked logic circuit is equipped to change process data received through the first interface. The circuit is equipped to output the changed process data in the local bus message.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: A file synchronization service generates a listing of files stored on a local data volume by executing a plurality of threads corresponding to directories of the data volume. Files to synchronize with a remote data storage service are identified based on comparison of the listed files with cached data indicative of files stored by the remote data storage service. A plurality of file synchronization requests are sent to the remote data storage service, where the plurality of files are sent in an order that is determined at least partly based on a scaling characteristic of the remote data storage service.

Abstract: Methods and systems for backing up and restoring different point in time versions of a virtual machine, a real machine, an application, a database, or a set of electronic files using a plurality of independently managed snapshot chains are described. The different point in time versions of the data being backed-up may be stored using two or more snapshot chains corresponding with two or more data partitions of the data being backed-up. Over time, additional full image snapshots may be acquired from an external server or generated locally by a storage appliance to limit the snapshot chain lengths and to limit the aggregate block chain lengths for the snapshot chains. Acquisition and generation of the additional full image snapshots may be staggered across different data partitions to limit computational and storage costs per snapshot.

Abstract: A bus system is provided. A bus system includes a slave functional block and a master functional block. The master functional block transmits a first command to the slave functional block. The slave functional block includes a first bus protector. The first bus protector receives the first command on behalf of the slave functional block and transmits a dummy signal corresponding to the first command to the master functional block in response to the slave functional block being in a state of not being able to receive the first command or not being able to transmit a response signal corresponding to the first command.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: An on-chip accelerator manager manages multiple accelerators in a programmable device. In one specific implementation, the multiple accelerators are identical accelerators. The accelerator manager and the multiple accelerators are deployed to the programmable device. One or more calls to a software library in a virtual function table are replaced with one or more calls to the on-chip accelerator manager. The on-chip accelerator manager receives an accelerator call, and in response, allocates the accelerator call to one of the multiple accelerators, performs load balancing to the multiple accelerators, and performs failover when one of the accelerators fails by allocating work that was allocated to the failed accelerator to a different accelerator. The on-chip accelerator can push work to the multiple accelerators in a first mode of operation, and the multiple accelerators can pull work from the on-chip accelerator manager in a second mode of operation.

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: A system for communicating between electronic devices on a communication bus includes a communication bus and one or more communication circuits each having an output driver coupled to the communication bus and each having an input terminal. Each communication circuit produces, in response to a request message, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communications from each communication circuit form a sequential data stream in response to the request message.

Abstract: This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.

Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

Abstract: Systems and methods provide concurrent access to a single input resource. An audio stack of a computing device can receive multiple requests from applications to provide concurrent access to audio data received via an input resource, such as audio data received via an audio card coupled to a microphone. A request to access the resource is received from a first application. Based on the request, a cache memory is instantiated to model a memory buffer of the resource. A direct session between a component of the audio stack and the resource is established. As audio data is encoded, the audio stack component can receive the encoded audio data and write the audio data into the cache. A first session between the first application and the cache is generated, such that the first application interprets the cache as the audio input resource buffer memory.

Abstract: Example embodiments relate to a method, a system, and a computer program product for load balancing for port selection. The method includes determining a processing load for each storage port in a plurality of storage ports having variable processing power and calculating a delay characteristic for each storage port of the plurality of storage ports according to its processing load. A command then may be sent to a selected storage port of the plurality of storage ports according to the delay characteristics and a policy.

Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

Abstract: A device that provides for the non-invasive data monitoring of analog IO of a Programmable Logic Controller (PLC) system is described. The output is ultimately presented to a user audibly and/or visually on an interface in real-time and is measured directly from the IO channel. This type of device allows the accurate reading and analysis of errors and erroneous data within a device and transmission of said data to disparate secondary devices for use.

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.