Abstract: Computing devices having slots and components for receipt of different types of peripherals are disclosed. According to an aspect, a computing device includes a body that defines an interior and comprises a rear wall defining a slot that extends into the interior. The slot is sized and shaped for receipt of two or more different types of peripherals. The computing device includes a motherboard that defines another slot being sized and shaped for receipt of the different types of peripherals. The other slot is substantially coplanar with the second slot. The computing device includes a connector operably interfaced with the motherboard and configured to interface with the different types of peripherals.

Abstract: Apparatuses, systems, and methods are disclosed for an output data path for non-volatile memory. A buffer may include a plurality of buffer stages. A buffer stage width may be a width of an internal bus for a non-volatile memory element. A buffer may include two or more read pointers, updated by an internal controller at different times in response to different portions of a clock signal. A parallel-in serial-out (PISO) component may receive data via an internal data path having a data path width equal to an internal bus width, and may output the data in a series of transfers controlled according to a clock signal, via an output bus having an output bus width narrower than an internal bus width. A PISO component may receive data from a portion of a buffer stage in response to an internal controller updating a read pointer to point to the buffer stage.

Abstract: A storage device includes a recording medium in which data is recorded on a cluster basis, and a memory that stores a file allocation table (FAT) in which disposition information regarding the cluster is recorded.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: In an example, there is disclosed a computing apparatus, having: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is higher in order than the first ordinal QoS profile; a slave; a multiplexed interconnect to communicatively couple the first master and second master to the slave with a priority according to the ordinal QoS profiles; and one or more logic elements, including at least one hardware logic element, providing a QoS engine to: determine that the first master has initiated a slave operation via the interconnect; determine that completing the slave operation according to a QoS criterion provided by the second master requires elevated QoS; and promote the first master to a third ordinal QoS profile having an order higher than the second ordinal QoS profile.

Abstract: A method of request scheduling in a computing environment comprises the following steps. One or more requests to at least one of read data from and write data to one or more storage devices in the computing environment are obtained from a host device. The one or more requests are aligned corresponding to a segment size for which one or more data services in the computing environment are configured to process data. The one or more aligned requests are dispatched to the one or more data services prior to sending the one or more requests to the one or more storage devices.

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract: There is provided a peripheral device including a multi-pole plug inserted into a jack of a jack device, the jack device including the jack, a conversion unit that converts a physical amount into an electrical signal or converts an electrical signal into a physical amount, a detection unit that detects whether the jack device is a corresponding device capable of handling multiplexed data obtained by multiplexing the electrical signal input and output to and from the conversion unit, a transmission and reception processing unit that transmits or receives the multiplexed data via a predetermined terminal of the multi-pole plug when the jack device is a corresponding device, and a function switching unit that performs assignment of an electrical function of a terminal other than the predetermined terminal of the multi-pole plug.

Abstract: A redundant external storage virtualization computer system. The redundant storage virtualization computer system includes a host entity for issuing an IO request, a redundant external SAS storage virtualization controller pair coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller pair through a SAS interconnect. The redundant storage virtualization controller pair includes a first and a second SAS storage virtualization controller both coupled to the host entity. In the redundant SAS storage virtualization controller pair, when the second storage virtualization controller is not on line, the first storage virtualization controller will take over the functionality originally performed by the second storage virtualization controller.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric. The method also includes establishing a peer-to-peer arrangement between the GPUs over the PCIe fabric by at least providing an isolation function in the PCIe fabric configured to isolate a device PCIe address domain associated with the GPUs from at least a local PCIe address domain associated with a host processor that initiates the peer-to-peer arrangement between the GPUs.

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

Abstract: An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.

Abstract: A data processing system includes host computers and a data storage system that (1) periodically calculates port congestion values for storage system ports based on per-port values for (a) a number of storage IO commands being processed by each port and (b) CPU utilization of one or more CPUs assigned to each port, and (2) periodically sends the port congestion values to the host computers. Each host computer includes multipathing logic for selectively directing storage IO commands on selected paths to the data storage system. The multipathing logic receives the port congestion values from the data storage system and utilizes the port congestion values for path selection by preferentially directing first storage IO commands of higher service level objective to storage system ports having lower congestion and preferentially directing second storage IO commands of lower service level objective to storage system ports having higher congestion.

Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.

Abstract: A bus interface unit for exchanging data via a bus system includes at least one bus control unit for connection to the bus system, having a control unit that is configured to output data received via the bus control unit from the bus system, and/or data derived therefrom, to an external unit, and/or to output data obtained from an external unit, and/or data derived therefrom, via the bus control unit to the bus system.

Abstract: A chipset implemented in a server node of a server system and including an embedded management controller (eMC) is disclosed. The eMC collects inner-node information of the server node for server system management. The eMC is coupled to a baseboard management controller (BMC) that is outside the server node and communicates with a remote console through a network. The eMC is specially designed for the corresponding server node to be differentiated from the other server nodes also coupled to the BMC. All eMCs coupled to the same BMC boot in a special way.

Abstract: In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.