Abstract: A controller may receive interface information, associated with one or more interfaces used to communicate with one or more components of a vehicle, and may receive application information associated with one or more applications configured to receive information from the one or more components via the one or more interfaces. The controller may store, based on the interface information and the application information, registration information that indicates whether the one or more applications are permitted to communicate via the one or more interfaces. The controller may receive, from an application of the one or more applications, a request for vehicle information from an interface of the one or more interfaces. The controller may verify whether the application is permitted to communicate via the interface, and may selectively route the request for the vehicle information to the interface based on verifying whether the application is permitted to communicate via the interface.

Abstract: An advanced PCI express board assembly is mountable in a PCI express slot. The assembly includes a main board that is attached to an adapter board by a connector section that includes mechanical and electrical connectors. When the main board is attached to the adapter board, the plane defined by the main board is parallel to, and laterally offset from, the plane defined by the adapter board. The adapter board is connectable to a female PCI express connector in the PCI slot. When the adapter board is connected to the female PCI express connector, the main board plane is perpendicular to the motherboard and is laterally offset from the PCI express slot. More and larger components can be placed on the main board while the assembly remains within the reserved PCI express space.

Abstract: In some examples, a first system may store a data object according to a first data protection level and may send the data object to a geographically remote second system for storing as a replicated data object. Based on determining that a condition for transitioning the data object to a different data protection level has been met, the first system may check a local data structure to determine that the data object was sent to the second system. Based on determining that the data object was sent for replication to the second system, the first system may send a request to the second system to verify storage of the replicated data object at the second system. Based on receiving a reply indicating storage of the replicated data object at the second system, the first system may transition the data object to the different data protection level.

Abstract: A system and method for insuring efficiency of a serial link between a host server and a switch is disclosed. A fabric switch has upstream ports associated with a serial link. A fabric controller is coupled to the switch. A host server includes a BIOS and a management controller. The host server has ports coupled to the serial link ports via cables to form lanes of the serial link. A memory is accessible by the controller and the management controller. The management controller reads an expected speed and width of the serial link from the memory. The BIOS determines an actual speed and width of the serial link. The management controller sends an error message if the actual speed and width do not match the expected speed and width.

Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

Abstract: An information processing apparatus includes a first bus interface to receive first data transferred in a pixel-parallel transfer mode, a second bus interface to receive second data transferred in a line-parallel transfer mode, a selector to select one of the first data transferred in the pixel-parallel transfer mode and the second data transferred in the line-parallel transfer mode, as input data, a transfer switching circuit to switch between the line-parallel transfer mode and the pixel-parallel transfer mode to process the input data according to the switched transfer mode.

Abstract: The invention is a microcircuit configured as a compact, radiation hardened, low-power general purpose I/O expander. The expander may be controlled by an external microcontroller or central processing unit through a serial interface. The expander provides a simple solution to miniaturize static parallel I/O signals using a simplified serial interface such as I2C or SPI.

Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data system is provided. The method includes initiating an isolation function in a communication fabric to form a peer arrangement between graphics processing units (GPUs) coupled to the communication fabric. The isolation function isolates a first address domain associated with the GPUs from at least a second address domain associated with the host by at least establishing synthetic devices representing the GPUs in the second address domain.

Abstract: An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

Abstract: A computing device configured to detect proper cable assembly to improve assembly and problem diagnosis is provided. The computing device includes a motherboard, a function board, and a middle plane connecting the motherboard and function board. The motherboard includes a baseboard management controller (BMC). The BMC is connected to I2C buses. The function board includes integrated circuits. The middle plane includes cable connections interconnecting the I2C buses that are connected to the BMC and the integrated circuits. The integrated circuits have unique system addresses that are identifiable by the BMC.

Abstract: An interface circuit provides communication between a memory card and a host device which use a half duplex communication protocol. The interface circuit switches communication direction between the host device and memory card by analyzing interface protocol. The interface circuit includes a sending packet analyzing module which receives a first signal packet from the host device and obtains working status of the host device and memory card by analyzing the first signal packet, a bus direction control module coupled to the sending packet analyzing module which generates a first control signal according to a first parameter in the first signal packet which includes conducting direction information indicating the host device between the memory card, and a direction switching module coupled to the bus direction control module which controls the conducting direction of the pathway between the host device and memory card according to the first control signal.

Abstract: Apparatus and methods for a USB hub connected to USB host and one or more USB devices to support the USB host and the USB devices to dynamically switch roles such that a product which initially operates as a USB device operates a USB host while a USB host supports additional operation as a USB device. Products such as smartphones, initially operating as USB devices, may dynamically switch roles to become USB hosts. Similarly USB hosts, such as PCs and in-vehicle infotainment systems, initially operating as USB hosts may dynamically support additional operation as USB devices. The USB host operates a USB device stack over a USB host stack such that the USB device stack communicates with a role-switched USB host via the root port that remains in a state acting as USB host. In addition, the USB host maintains a connection to an upstream port of the USB hub.

Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.

Abstract: A mechanism for enumerating Peripheral Component interconnect (PCI) Express (PCIe) devices within a data processing system is provided. Responsive to a reset of the data processing system, Peripheral Component interconnect (PCI) enumeration information for a set of PCIe devices coupled to the data processing system is read from a processor register. The PCI enumeration information is stored in an address space. PCI enumeration of the PCIe devices is skipped and the PCI enumeration information stored in the address space is presented to the operating system (OS) of the data processing system in order that the OS maintaining the PCIe devices using the PCI enumeration information.

Abstract: An example method to hide a presence of a storage device is provided herein. The method masks the presence of the storage device using a microcontroller that controls a presence bit. The method unmasks the presence of the storage device using the array controller to instruct the microcontroller to change the value of the presence bit after installation is complete.

Abstract: Embodiment of the present disclosure provides a system, a computer program product and a method for managing a peripheral component interface express device hotplug by receiving an operation command from a user through a user command interface module; sending, in response to reception of the operation command, the operation command to a hotplug management module via an interface provided by a hotplug interface library; and performing, by the hotplug management module, the operation command by means of at least one of an interface provided by an operating system, a kernel of the operating system, and at least one of a corresponding plurality of hotplug group service modules, in response to receiving the operation command.

Abstract: A method to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without OTG controllers or additional vehicle wiring, or inhibiting the functionality of any consumer devices connected to the same USB Hub. Preferably, the method is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The method can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port. In the case where the consumer device is acting as a USB Host, signals between the consumer device and the vehicle's embedded USB Host are processed through a USB bridge, thereby rendering the consumer device compatible with the vehicle's embedded USB Host.

Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.