Abstract: A network system for identifying a cable connection is provided. The network system includes a management server, a server device, and a storage device. The management server includes system-management software. The server device is connected to the management server. The server device includes a BMC configured to communicate with the system-management software of the management server. The storage device includes at least one cable port configured to receive a storage cable that connects the storage device to the server device. The cable port includes a non-volatile memory, an indicator light, and a I2C bus.

Abstract: The present invention is an SPI-communication-method communication apparatus that has a plurality of slave communication units for a single master communication unit and an electric power converter utilizing the communication apparatus; the master communication unit outputs communication signals simultaneously to all of the slave communication units and separately reads respective data signals outputted by the slave communication units, in accordance with a priority.

Abstract: A processing module of a memory storage unit includes an interface configured to interface and communicate with a communication system, one or more memory devices, and processing circuitry operably coupled to the interface and to the memory that is configured to receive an access request from a distributed storage network (DSN) client and determine whether a quality of service (QoS) identity for the DSN client is associated with the access request. Based on a determination that a QoS identity is associated with the access request, the processing module determines a QoS level associated with the access request, where the QoS level is based at least in part on the QoS identity that is associated with the access request. The processing module maps the QoS level to a storage layer priority for the access request and transmits the storage layer priority for execution by at least one of the one or more memory devices.

Abstract: The present disclosure relates generally to improved systems and methods for control of a first-in, first-out (FIFO memory). More specifically, the present disclosure relates to improved timing and/or control signals used to control operation of the FIFO memory. For example, access circuitry of the memory device may pulse a control signal used to control latching of data at the FIFO memory. Further, the access circuitry may pulse one or more bits of a column address bus to generate a column address corresponding to data to be latched at the FIFO memory. Accordingly, the current, power, and/or area consumed by the memory device may be reduced.

Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage card insertable into a host system includes a plurality of storage device connectors in a stacked arrangement, each configured to mate with associated storage devices and carry Peripheral Component Interconnect Express (PCIe) signaling for the associated storage devices. The storage card also includes a PCIe switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.

Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage card insertable into a connector of a host system includes a plurality of M.2 device connectors in a stacked arrangement comprising a first horizontal row of one or more M.2 device connectors positioned vertically higher in the stacked arrangement than a second horizontal row of one or more M.2 device connectors, the plurality of M.2 device connectors each configured to mate with associated M.2 devices. The storage card also includes a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the plurality of M.2 device connectors and a connector of the storage card, wherein the PCIe switch circuit is configured to receive storage operations over the connector of the storage card and transfer the storage operations for delivery to ones of the plurality of M.2 device connectors over associated PCIe interfaces.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: A storage virtualization computer system. The storage virtualization computer system comprises a host entity for issuing an IO request, a storage virtualization controller coupled to the host entity for executing IO operations in response to the IO request, and a at least one physical storage device, each coupled to the storage virtualization controller through a point-to-point serial-signal interconnect, for providing storage to the storage virtualization computer system through the storage virtualization controller. As an example, the point-to-point serial-signal interconnect can be a Serial ATA IO device interconnect.

Abstract: An electronic device and method for communicating with an external electronic device that is connected via a connector of the electronic device are provided. The electronic device includes a connector including a first pin and a second pin, a communication interface connected with the connector, and at least one processor electrically connected with the communication interface, wherein the at least one processor may be configured to apply a first current to the first pin, determine whether liquid is introduced into the connector using the second pin, and if the liquid is introduced into the connector, apply a second current smaller than the first current to the first pin.

Abstract: An automation device has a main module and an interchangeable connection module in which a fieldbus port of the automation device is located. The automation device is characterized in that the interchangeable connection module contains a non-volatile memory which can be read out by the main module of the automation device. A method for operating the automation device includes the steps of connecting a main module of the automation device with a connection module, reading the non-volatile memory of the connection module, detecting any incompatibilities between the main module and the connection module, and placing the automation device in operation if no incompatibilities are detected.

Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device emulates a USB device. The embedded-system device exposes the emulated USB device to a host of the embedded-system device through a USB connection. The embedded-system device receives data from BIOS of the host through the emulated USB device.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.

Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.