Patents Examined by Fernando Hidalgo
  • Patent number: 10665607
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10658062
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10656605
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a target sequence from a source sequence. In one aspect, the system includes a recurrent neural network configured to, at each time step, receive am input for the time step and process the input to generate a progress score and a set of output scores; and a subsystem configured to, at each time step, generate the recurrent neural network input and provide the input to the recurrent neural network; determine, from the progress score, whether or not to emit a new output at the time step; and, in response to determining to emit a new output, select an output using the output scores and emit the selected output as the output at a next position in the output order.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 19, 2020
    Assignee: Google LLC
    Inventors: Chung-Cheng Chiu, Navdeep Jaitly, Ilya Sutskever, Yuping Luo
  • Patent number: 10650893
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: May 12, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Patent number: 10651300
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 12, 2020
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao
  • Patent number: 10643119
    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
  • Patent number: 10643681
    Abstract: The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic (SyAF) layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, SyAF layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the SyAF layers to grow in the FCC (111) direction.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 5, 2020
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 10636510
    Abstract: A semiconductor device includes a fuse array circuit including a plurality of fuse cell arrays, and configured to output fuse data based on one or more fuses that have been ruptured or not within a fuse cell array; and a fuse control circuit configured to compare the fuse data and one or more failure addresses, and re-perform a rupture operation for the fuse cell array when the fuse data and the failure addresses indicate a difference between the fuse data and the failure addresses.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Joohyeon Lee
  • Patent number: 10629252
    Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 10623004
    Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
  • Patent number: 10614868
    Abstract: A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Borna J. Obradovic, Ryan M. Hatcher, Titash Rakshit
  • Patent number: 10607682
    Abstract: A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: I Yeong Jung, Geun Il Lee
  • Patent number: 10607703
    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hsuan Liang, Jeng-Wei Yang, Man-Tang Wu, Nhan Do, Hieu Van Tran
  • Patent number: 10607677
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura
  • Patent number: 10600478
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag
  • Patent number: 10598709
    Abstract: Nodes within a wireless mesh network are configured to monitor time series data associated with a utility network (or any other device network). One or more servers coupled to the wireless mesh network configures a data ingestion cloud to receive and process the time series data from the nodes to generate data streams. The server(s) also configure a distributed processing cloud to perform historical analysis on data streams, and a real-time processing cloud to perform real-time analysis on data streams. The distributed processing cloud and the real-time processing cloud may interoperate with one another in response to processing the data streams. Specifically, the real-time processing cloud may trigger a historical analysis on the distributed processing cloud, and the distributed processing cloud may trigger real-time processing on the real-time processing cloud. Any of the processing clouds may encompass edge nodes configured to perform real-time processing and generate data streams.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 24, 2020
    Assignee: ITRON NETWORKED SOLUTIONS, INC.
    Inventors: Charles P. Sum, George H. Flammer, III
  • Patent number: 10593396
    Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 17, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Michail Tzoufras, Marcin Gajek
  • Patent number: 10586586
    Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyuseok Lee, Sangmin Hwang, Si-Woo Lee
  • Patent number: 10586585
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 10, 2020
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10586606
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal