Abstract: A method of manufacturing a display apparatus includes forming a thin-film transistor on a substrate and forming a planarization layer to cover the thin-film transistor, forming, on the planarization layer, a pixel electrode electrically connected to the thin-film transistor and a pixel defining layer exposing at least a center portion of the pixel electrode, and defining at least one groove having a closed curve shape at a location corresponding to a second non-display area. When the thin-film transistor is formed, a voltage line is also formed at a location corresponding to a first non-display area. When the at least one groove is formed, a portion of the planarization layer disposed between the pad area and the display area is simultaneously removed such that a portion of the voltage line between the pad area and the display area is exposed.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate; a plurality of light emitting units on the base substrate, where the plurality of light emitting units include a plurality of pixel display areas; and a reflection layer on the base substrate. The reflection layer includes a plurality of patterns and a plurality of openings defined between adjacent patterns of the plurality of patterns, and positions of the plurality of openings are corresponding to positions of the plurality of pixel display areas.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semicondu

Abstract: A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.

Abstract: A display substrate includes a base substrate and an encapsulation film disposed at a first side of the base substrate. At least one corner of an edge of the encapsulation film is a rounded corner or a substantially rounded corner.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface. A semiconductor chip is on the first surface of the substrate. A passive element is on the second surface of the substrate. The substrate includes a first passive element pad and a second passive element pad that are exposed by the second surface. A dam extends downwardly from the second surface. The dam includes a first dam and a second dam. The passive element is disposed between the first dam and the second dam. The passive element includes a first electrode portion electrically connected to the first passive element pad. A second electrode portion is electrically connected to the second passive element pad.

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

Abstract: There is provided a display element, including: a display region including pixels arranged in a two-dimensional form, each of the pixels including a plurality of sub pixels. In each pixel, a height of a light reflecting portion with respect to a light emitting portion is adjusted for each sub pixel.

Abstract: According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

Abstract: A semiconductor device includes semiconductor modules disposed on a support member via a cooling plate; and a metal plate which supports a control board for controlling the semiconductor modules, wherein the metal plate, being supported by the support member, covers the semiconductor modules, and also fixes the control board opposite the installation surfaces of the semiconductor modules.

Abstract: In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.

Abstract: Disclosed is a light emitting panel and a display device. The light emitting panel includes a substrate, wherein the substrate comprises a display area, a non-display area and a bending area connecting the display area and the non-display area; a transistor layer, wherein the transistor layer is disposed on the substrate and disposed relative to the display area and the non-display area; an organic layer, wherein the organic layer is disposed on the substrate and disposed relative to the bending area; and a wiring layer, wherein the wiring layer is disposed on the organic layer; wherein a vertical height of the organic layer is greater than a vertical height of the transistor layer.

Abstract: An organic light emitting device and a method of manufacturing the same are provided. The organic light emitting device, from bottom to top, includes a substrate, an indium tin oxide layer, a semiconductor layer, and a pixel defining layer. The semiconductor layer covers foreign particles on the indium tin oxide layer to make the indium tin oxide layer have an even thickness. The method of manufacturing the organic light emitting device including steps of providing an indium tin oxide layer, providing a semiconductor layer, patterning, and providing a pixel defining layer. The disclosure prevents from uneven brightness (mura) causing from a bright spot or a dark spot appearing at the foreign particles and ensures an overall even brightness of the organic light emitting device by providing the semiconductor layer disposed on the indium tin oxide layer to cover foreign particles on the indium tin oxide layer.

Abstract: A dual-diaphragm differential capacitive microphone includes: a back plate, a first diaphragm, and a second diaphragm. The first diaphragm is insulatively supported on a first surface of the back plate, where the back plate and the first diaphragm form a first variable capacitor. The second diaphragm is insulatively supported on a second surface of the back plate, where the back plate and the second diaphragm form a second variable capacitor. The back plate is provided with at least one connecting hole. The second diaphragm is provided with a recess portion recessed towards the back plate, where the recess portion passes through the connecting hole and is connected to the first diaphragm. The dual-diaphragm differential capacitive microphone achieves a higher signal-to-noise ratio.

Abstract: According to an aspect of the present disclosure, a light emitting display device includes a substrate defined by a plurality of sub-pixels and a first overcoating layer disposed on the substrate, a connection electrode and a sacrificial layer disposed on the first overcoating layer, a first electrode disposed on the connection electrode, a second overcoating layer disposed on the sacrificial layer and including an opening that exposes a portion of the first electrode, a dummy first electrode disposed on a top surface of the second overcoating layer and a side surface of the opening and separated from the first electrode, a bank layer covering the dummy first electrode and a portion of the first electrode, and an emission layer and a second electrode disposed on the first electrode and the bank layer.