Patents Examined by Fetsum Abraham
  • Power factor correction circuit with high-voltage semiconductor component
    Patent number: 6819089
    Abstract: A switching power supply including a power factor correction circuit comprises a rectifier, an inductor coupled in series with the rectifier, a semiconductor switch formed by a compensation device coupled in parallel with the rectifier and the inductor. The output circuit comprises a diode coupled in series with a capacitor both coupled in parallel with the semiconductor switch. An input current sensor, and a control unit for controlling the compensation device are provided.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: November 16, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Protection of an integrated circuit against electrostatic discharges and other overvoltages
    Patent number: 6818953
    Abstract: The forming of an integrated circuit including at least one element of electronic protection of the circuit formed of at least one switch for short-circuiting supply conductors arranged in a rail, the switch being integrated in the rail, under said conductors.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: November 16, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Alexandre Malherbe, Fabrice Blisson
  • Buried gate-field termination structure
    Patent number: 6818947
    Abstract: In a power semiconductor device 10, a continuous trench has an outer circumferential portion 58 that includes a field plate and inner portions 28 that carry include one or more gate runners 34 to that the gate runners and the field plate are integral with each other. The trench structure 58, 28 is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: November 16, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Christopher B. Kocon, Rodney S. Ridley, Sr., Gary M. Dolny, Nathan Lawrence Kraft, Louise E. Skurkey
  • Dual gate MOSFET
    Patent number: 6815772
    Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 9, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Laser alignment target and method
    Patent number: 6815838
    Abstract: A laser alignment target is provided having a surface that is out of plane with and has substantially the same first reflectivity as an adjacent surface of the semiconductor device, and a sidewall having a second reflectivity different than the first reflectivity. The target provides sidewalls that provide contrast for finding the target despite loss of contrast created by layers of dielectric over the target and use of short wavelength light.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Richard A. Gilmour, William T. Motsiff, Christopher D. Muzzy
  • Multi-color light emitting diode package
    Patent number: 6812498
    Abstract: Disclosed herein is a multi-color light emitting diode package. The multi-color light emitting diode package mounted thereon with at least three light emitting diodes comprises a substrate formed at the upper surface thereof with a pattern including three first terminals, and a single second terminal, first and second light emitting diodes, the diodes being mounted on a conductive mount pattern extending from the second terminal, and all formed at their upper surfaces with first and second electrodes, and a single zener diode chip having two zener diodes, the zener diode chip being mounted on the conductive mount pattern, and formed at a lower surface thereof with a single second electrode, and at an upper surface thereof with two first electrodes.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 2, 2004
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seoung Ju Moon
  • Polysilicon linewidth measurement structure with embedded transistor
    Patent number: 6812506
    Abstract: A semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the multiple parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias extending to the gate electrode line and the source/drain regions. A method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hormuzdiar E. Nariman, Derick J. Wristers
  • TFT type optical detecting sensor implementing different TFTs and the fabricating method thereof
    Patent number: 6812054
    Abstract: A thin film transistor optical detecting sensor includes an array substrate having a transparent substrate, a plurality of sensor thin film transistors disposed on the transparent substrate, each having a first silicon layer of a first thickness, a plurality of storage capacitors, each connected with a corresponding one of the plurality of sensor thin film transistors, storing charges of an optical current, and a plurality of switch thin film transistors, each having a second silicon layer of a second thickness less than the first thickness.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: November 2, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: In-Su Joo
  • SOI based bipolar transistor having a majority carrier accumulation layer as subcollector
    Patent number: 6812533
    Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Qiqing Ouyang
  • Liquid crystal display devices having fill holes and electrical contacts on the back side of the die
    Patent number: 6809337
    Abstract: A method of fabricating LCOS devices and testing them at the wafer-scale to identify known-bad dice, to facilitate completing fabrication of only known-good dice. A wafer-scale transparent electrode glass is temporarily placed over the wafer, and liquid crystal material is injected into the LCOS device cavities through fill holes extending through the wafer. After removing the glass and separating the wafer into dice, only the good dice have their die-scale glass attached, liquid crystal material re-injected, solder bumps affixed, and substrate attached.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: October 26, 2004
    Assignee: Intel Corporation
    Inventor: Paul Winer
  • Semiconductor device and operation method thereof
    Patent number: 6806525
    Abstract: A semiconductor device with a non-volatile memory, having: first to fourth memory cells arranged in a first direction; a first bit line extending over the first memory cell in a second direction and connected to the second memory cell; a second bit line extending over the second memory cell in the second direction and connected to the first memory cell; a third bit line extending over the third memory cell in the second direction and connected to the third memory cell; and a fourth bit line extending over the fourth memory cell in the second direction and connected to the fourth memory cell.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: October 19, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Takeuchi, Riichiro Shirota
  • Recessed magnetic storage element and method of formation
    Patent number: 6806527
    Abstract: A method of forming self-aligned recessed MRAM structures is disclosed. Recessed pinned and sense magnetic layers of an MRAM stack are formed in recessed digit lines formed in an insulating layer.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: October 19, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Insulated gate field effect semiconductor devices and method of manufacturing the same
    Patent number: 6803600
    Abstract: An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The gate electrode is then anodic oxidized to form an oxide film enclosing the electrode. With the oxide film as a mask, highly doped regions are formed by ion implantation in order to define lightly doped regions between the highly doped regions and the channel region located therebetween.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: October 12, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang
  • Transistor having a graded active layer and an SOI based capacitor
    Patent number: 6798021
    Abstract: By ion implantation process, a P-type impurity for element isolation is implanted at an impurity concentration (P1) into a silicon layer (3) defined between the bottom surface of an element isolation insulating film (5a) and the upper surface of a BOX layer (2). Resulting from this implantation, a P-type impurity is implanted at an impurity concentration (P2) into the silicon layer (3) under a gate oxide film (7a) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2). Under a capacitor dielectric film (7b) and in the vicinity of an interface between the silicon layer (3) and the BOX layer (2), the silicon layer (3) has an impurity concentration (P0) which is the initial concentration of itself.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 28, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • DRAM cell structure capable of high integration and fabrication method thereof
    Patent number: 6797590
    Abstract: A DRAM cell structure capable of high integration includes a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate, and a transistor being formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor. A method for fabricating a DRAM cell structure capable of high integration includes the steps of (a) forming a trench vertically and cylindrically in a silicon substrate, (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench, (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: September 28, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Cheolsoo Park
  • Annular gate and technique for fabricating an annular gate
    Patent number: 6794699
    Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: September 21, 2004
    Inventors: Lucien J. Bissey, Kevin G. Duesman, Warren M. Farnworth
  • Group III nitride compound semiconductor light-emitting element
    Patent number: 6794690
    Abstract: A Group III nitride compound semiconductor light-emitting element (flip chip type light-emitting element) provided with a p-side electrode and an n-side electrode formed on one surface side, wherein the p-side electrode includes: a first metal layer containing Ag and formed on a p-type semiconductor layer; a protective film with which the first metal layer except a part region is covered; and a second metal layer not containing Ag and formed on the protective film.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 21, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Toshiya Uemura
  • Semiconductor device with porous interlayer insulating film
    Patent number: 6794754
    Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate. Then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a gas mixture containing an oxygen gas in a chamber.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 21, 2004
    Inventors: Hiroshi Morisaki, Shinji Nozaki
  • Compound semiconductor having a doped layer between the gate and an ohmic contact of an active region
    Patent number: 6787817
    Abstract: The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Hiroyuki Takazawa, Shinichiro Takatani, Masao Yamane, Masayoshi Kobayashi
  • Semiconductor memories
    Patent number: 6787835
    Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: September 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Bryan Atwood, Kazuo Yano, Tomoyuki Ishii, Taro Osabe, Kazumasa Yanagisawa, Takeshi Sakata