Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.

Abstract: A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.

Abstract: Disclosed herein is a display device, including a display element, a first scanning line, a second scanning line, a data signal line, a switching element having a first terminal and a second terminal of a first conduction type, the first terminal being connected to the data signal line, for being held in a conducting state or a non-conducting state according to a voltage applied to the first scanning line, and a storage capacitance having a first electrode and a second electrode that shares the second scanning line, wherein the second terminal of the switching element is connected to the display element and connected to the first electrode of the storage capacitance including a semiconductor film of a second conduction type different from the second terminal.

Abstract: A three-dimensional Triple-Gate (Tri-gate) device having a three-sided strained silicon channel and superior drive current is provided. The Tri-gate device includes a composite fin structure consisting of a silicon germanium core and a three-sided strained silicon epitaxy layer grown from surface of said silicon germanium core. A gate strip wraps a channel portion of the composite fin structure. Two distal end portions of the composite fin structure not covered by the gate strip constitute source/drain regions of the Tri-gate device. A high quality gate insulating layer is interposed between the composite fin structure and the gate strip.

Abstract: A thin film transistor array fabricated on a polyimide substrate forms a backplane for an electronic display. The thin film transistor array incorporates gate electrodes, a gate insulating layer, semiconducting channel layers deposited on top of the gate insulating layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer. An insulating encapsulation layer is positioned on the channel layer. The layers are deposited onto the polyimide substrate using PECVD and etched using photolithography to form the backplane.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: A structure of a non-volatile flash memory, in which a punch-through current is suppressed and the area of a memory cell is reduced, is provided. The non-volatile flash memory being a NOR type non-volatile flash memory provides floating gates and a common source line, and drains. And at the structure of the non-volatile flash memory, a region overlapped one of the drains and one of the floating gates in a memory cell is larger than a region overlapped the common source and one of the floating gates in the memory cell.

Abstract: Thin-film transistor display devices include composite electrodes which provide low resistance contacts and paths for electrical signals and are less susceptible to parasitic metal migration which can limit display quality and lifetime. In particular, a thin-film transistor (TFT) display device is provided having an insulated gate electrode on a face of a substrate (e.g., transparent substrate) and a semiconductor layer on the insulated gate electrode, opposite the face of the substrate. Spaced apart source and drain electrodes are also provided on the semiconductor layer. These source and drain electrodes each preferably comprise a composite of at least two layers containing respective metals therein of different element type. Preferably, one of the layers comprises a metal which is capable of forming a low resistance contact with electrodes such as a pixel electrode (e.g.

Abstract: The luminous efficiency of a nitride semiconductor device comprising a gallium nitride-based semiconductor layer formed on a dissimilar substrate is improved. An n-type layer formed on the substrate with a buffer layer interposed between them comprises a portion of recess-and-projection shape in section as viewed in the longitudinal direction. Active layers are formed on at least two side faces of the projection with the recess located between them. A p-type layer is formed within the recess. An insulating layer is formed on the top face of the projection, and on the bottom face of the recess. The n-type layer is provided with an n-electrode while the p-type layer is provided with a p-electrode contact layer. As viewed from the p-type layer formed within the recess in the gallium nitride-based semiconductor layer, the active layer and the n-type layer are located in an opposite relation to each other.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a pitch X, and an insulation layer 36 having a specified film thickness covers upper portions of the fuses 20. The fuses 20 may have a width W and a film thickness T that have a relation indicated by the following equation: T?0.4/W. Furthermore, the width W of the fuse 20 may be 3 ?m or less, and may be less than ½ of the pitch X of the fuses 20. Also, the film thickness of the fuse 20 may be 0.7 ?m or less.

Abstract: A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide.

Abstract: A method for manufacturing a semiconductor device is provided including: a step of forming a solid barrier metal layer on an interlayer insulating film; a removing step of removing at least a part of the solid barrier metal layer located at a place at which a pad opening portion is to be formed; a step of forming a solid second Al alloy film on the interlayer insulating film exposed in the removing step described above and the solid barrier metal layer; a step of patterning the solid second Al alloy film and the solid barrier metal layer so as to form a bonding pad portion on the interlayer insulating film; a step of forming a passivation film on the bonding pad portion and the interlayer insulating film; and a step of forming the pad opening portion in the passivation film at a position located on the bonding pad portion.

Abstract: An opaque, low resistivity silicon carbide and a method of making the opaque, low resistivity silicon carbide. The opaque, low resistivity silicon carbide is a free-standing bulk material that may be machined to form furniture used for holding semi-conductor wafers during processing of the wafers. The opaque, low resistivity silicon carbide is opaque at wavelengths of light where semi-conductor wafers are processed. Such opaqueness provides for improved semi-conductor wafer manufacturing. Edge rings fashioned from the opaque, low resistivity silicon carbide can be employed in RTP chambers.

Abstract: A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.

Abstract: This invention discloses the several means by which transient noise due to capacitance related displacement current can be excluded from the optical signal coming from a silicon detector used in opto-couplers. The exclusion of such noise permits a high degree of detector sensitivity which permits the use of low efficiency silicon based LEDs for opto-coupler applications.

Abstract: In an optoelectronic component assembly and a method for the production thereof, the optoelectronic component assembly includes an optoelectronic component arranged on a support element, which is surrounded by a closed dam. An encapsulation is arranged in an inner area of the dam, which encapsulates the optoelectronic component and includes two sealing materials. The inner area of the dam may be filled with a first sealing material up to the top edge of the optoelectronic component. The inner area of the dam located above the optoelectronic component is filled with a second transparent sealing material at least in one area of the window.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields. The SRAM cell comprises cross coupled pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply VDD, and the N1, N2 devices being coupled through a P+ diffusion region to ground. A first passgate is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline.

Abstract: A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.