Abstract: A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed below of the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in magnetic flux of the inductor.

Abstract: An integrated circuit device and methods of producing such device. The device has a substrate, e.g., silicon. An insulating layer is formed overlying the substrate. A copper metal layer is overlying the insulating layer. The device also has an etch stop layer overlying the copper metal layer and an interlayer dielectric material overlying the etch stop layer. The interlayer dielectric material includes an upper surface. A plurality of via openings are defined within a region of the interlayer dielectric layer from the upper surface through the etch stop layer to the copper metal layer. The device has a copper fill material within each of the plurality of via openings to define a plurality of copper structure extending from the upper surface through the etch stop layer to the copper metal layer. A first barrier metal layer is overlying each of the plurality of copper structures to define a first electrode of a capacitor structure.

Abstract: A self-assembled nanobump array structure including a semi-absorbing outer layer provided on at least one nanobump-forming substrate layer, the semi-absorbing outer layer configured to ablate slowly to allow an applied laser energy to be transmitted to the at least one nanobump-forming substrate layer, in which the self-assembled nanobump array structure is formed by an energy and a pressure buildup occurring in the at least one nanobump-forming substrate layer.

Abstract: A camera module for a mobile device is reduced in size and manufacturing cost. A filter material made of a multi-layer thin film is bonded to a surface of a lens which is bonded to a surface of an image sensor chip. The filter material is a filter to block radiation within a predetermined range of wave length in an incident radiation to the lens, for example, an IR filter to block infrared radiation. An iris material made of a film such as an acrylic film or a polyolefin film is bonded to the lens covered with the filter material.

Abstract: A good interface characteristic can be maintained, and a leakage current of a dielectric film can be decreased. A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a gate dielectric film containing at least nitrogen and a metal, the gate dielectric film being formed on the semiconductor substrate, and including a first layer region contacting the semiconductor substrate, a second layer region located at a side opposite to that of the first layer region in the gate dielectric film, and a third layer region located between the first and second layer regions, a maximum value of a nitrogen concentration in the third layer region being higher than maximum values thereof in the first and second layer regions; a gate electrode contacting the second layer region; and a pair of source and drain regions formed at both sides of the gate dielectric film in the semiconductor substrate.

Abstract: A semiconductor integrated circuit device is formed by a semiconductor substrate having an SiGe layer and a first Si layer epitaxially grown thereover, and on which there are element formation regions each partitioned by element isolation regions; a shallow groove isolation, which has a groove formed in each of the element isolation regions and an insulating film inside of the groove, said groove penetrating through the first Si layer and having a bottom in the SiGe layer; a second Si layer formed between the shallow groove isolation and the SiGe layer; and a semiconductor element formed over the main surface of the semiconductor substrate in the element formation regions. This construction enables a reduction in leakage current via the walls of the shallow groove isolation of the strained substrate, thereby improving the element isolation properties.

Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list.

Abstract: In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract: A semiconductor device such as a photodetector has a substrate having an active region layer containing an active region of the device. A dielectric layer is disposed on the active region layer, and a metal active region contact is disposed in the dielectric layer above the active region and electrically contacting the active region. A metal electrostatic discharge (ESD)protection structure is disposed in the dielectric layer around the active region contact, wherein the ESD protection structure electrically contacts the active region layer of the substrate to provide an ESD discharge path for charge on the surface of the dielectric layer.

Abstract: An electro-optical device includes, above a substrate, data lines extending in a first direction, scanning lines which extend in a second direction and which cross the data lines, pixel electrodes and thin film transistors disposed so as to correspond to regions in which the data lines and the scanning lines cross, storage capacitors electrically connected to the thin film transistors and the pixel electrodes, and a shield layer disposed between the data lines and the pixel electrodes. An upper electrode and a lower electrode between which a dielectric film forming each storage capacitor is supported including a first portion laminated along a plane parallel with one surface of the substrate and a second portion laminated along a plane orthogonal to the surface of the substrate, the sectional shape of the capacitor including a projecting shape.

Abstract: In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (&egr;) in the form of parallel strip-like electrical conductors in each layer, the electrodes (&egr;) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: The present invention concerns an integrated variable capacitance device comprising at least one membrane (12) forming at least one mobile armature and having at least one principal face facing at least one fixed armature. In accordance with the invention, the membrane has at least one rigidity rib (32) lying in a perpendicular direction to said principal face. Application in the production of resonant filters.

Abstract: The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die. The invention also encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.