Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip.

Abstract: A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices.

Abstract: An optoelectronic device having an optoelectronic component that receives or generates radiation and has a main radiation passage surface, wherein the component is assigned an aperture which defines a radiation cone for radiation passing through the main radiation passage surface, and the aperture has an inner surface having a region inclined away from the main radiation passage surface.

Abstract: A method of manufacturing a light emitting diode (LED) substrate includes following steps: providing a nano-patterned substrate, which has a plurality of convex portions and a plurality of first concave portions that are spaced apart from each other, wherein each first concave portion has a depth (d1); forming a plurality of protection structures to cover each convex portion, and exposing a bottom surface of each first concave portion; performing an anisotropic etching processing to etch the bottom surface of each first concave portion which is not covered by the protection structure so as to form a plurality of second concave portions having a depth (d2), and d2 is greater than d1.

Abstract: Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.

Abstract: Exemplary embodiments of the present invention provide a method of growing a nitride semiconductor layer including growing a gallium nitride-based defect dispersion suppressing layer on a gallium nitride substrate including non-defect regions and a defect region disposed between the non-defect regions, and growing a gallium nitride semiconductor layer on the defect dispersion suppressing layer.

Abstract: A photodetector may have a structure including conductive patterns and an intermediate layer interposed between the conductive patterns. A length L of at least one side of the second conductive pattern that overlaps the first conductive pattern and the intermediate layer satisfies the equation L=?/2neff, wherein the neff is an effective refractive index of a surface plasmon waveguide formed of the first conductive pattern, the intermediate layer, and the second conductive pattern during a surface plasmon resonance. Heat generated in the intermediate layer when the electromagnetic wave having the wavelength ? is incident thereon generates a current variation.

Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.

Abstract: This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; a first light-emitting stack comprising a first active layer; a bonding interface formed between the substrate and the first light-emitting stack; and a contact structure formed on the first light-emitting stack and comprising first, second and third contact layers. Each of the first, second and third contact layers comprises a doping material.

Abstract: Embodiments of the present invention provide an array substrate, a method for manufacturing the same and a display device. The method for manufacturing a thin film transistor array substrate comprises: forming a passivation layer and a resin layer on a substrate in sequence; removing a part of the resin layer through a patterning process, so as to form a resin-layer via hole passing through the resin layer; etching the passivation layer under the resin-layer via hole, so as to form a via hole passing through the resin layer and the passivation layer; treating the via hole with an etching process, so that a sidewall at the resin layer and a sidewall at the passivation layer for the via hole smoothly adjoin.

Abstract: A super junction semiconductor device includes strip structures between mesa regions that protrude from a base section in a cell area. Each strip structure includes a compensation structure with a first and a second section inversely provided on opposing sides of a fill structure. Each section includes a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The strip structures extend into an edge area surrounding the cell area. In the edge area the strip structures include end sections. The end sections may be modified to enhance break down voltage characteristics, avalanche ruggedness and commutation behavior.

Abstract: Example embodiments disclose transistors, methods of manufacturing the same, and electronic devices including transistors. An active layer of a transistor may include a plurality of material layers (oxide layers) with different energy band gaps. The active layer may include a channel layer and a photo sensing layer. The photo sensing layer may have a single-layered or multi-layered structure. When the photo sensing layer has a multi-layered structure, the photo sensing layer may include a first material layer and a second material layer that are sequentially stacked on a surface of the channel layer. The first layer and the second layer may be alternately stacked one or more times.

Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.

Abstract: A barrier-type photo-detector, such as an infra-red detector, is disclosed. The detector may include an absorber layer having predetermined majority and minority carrier types with corresponding energy bands; and a Barrier made, at least in part, of a semiconductor with a Barrier energy gap and corresponding conduction and valence bands, a first side of said Barrier adjacent a first side of said absorber layer. Metal contact regions may be disposed on the barrier layer, the metal contact regions delineating pixels where image data may be read out from the photo-detector; wherein the Barrier is configured so as to allow minority carrier current flow while blocking majority carrier current flow between the absorber layer and the metal contact regions.

Abstract: Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling.

Abstract: A light-emitting device includes a substrate, a light-emitting element mounted on a first flat surface of the substrate, and a glass sealing member for sealing the light-emitting element, wherein the sealing member is in contact with the first flat surface and a side surface of the substrate and a second flat surface of the surface opposite to the first flat surface is exposed.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: An OLED display includes: a substrate; a first signal line provided on the substrate; a second signal line crossing the first signal line; a thin film transistor connected to the first signal line and the second signal line; a pixel electrode connected to a drain electrode of the thin film transistor; an emission layer formed on the pixel electrode; a common electrode formed on the emission layer and formed of a reflective material; and a capacitor overlapping the pixel electrode.

Abstract: A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The compensation structure lines at least sidewall portions of compensation trenches that extend between semiconductor mesas along a vertical direction perpendicular to a first surface of the semiconductor portion. Within the super junction structure and a pedestal layer that may adjoin the super junction structure, a sign of a lateral compensation rate changes along the vertical direction resulting in a local peak of a vertical electric field gradient and to improved avalanche ruggedness.