Patents Examined by Gene M. Munson
  • Electronic devices with diffusion barrier and process for making same
    Patent number: 6465887
    Abstract: An epitaxial barrier material provides not only a unique growth medium for growing single crystal structures of elemental metal thereon, but also provides an effective diffusion barrier at extremely thin thicknesses against migration of atoms from the metallization layer into an adjacent semiconductor substrate or low dielectric insulation layer. This invention is particularly advantageous for forming single crystal, transition metal conductor lines, contacts, filled trenches, and/or via plugs, and especially conductor structures based on transition metals of copper, silver, gold, or platinum. These metals are highly attractive for interconnect strategies on account of there respective low resistivity and high reliability characteristics. Processes for making the barrier film in a semiconductor device are also covered.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: October 15, 2002
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Tak Kin Chu, Francisco Santiago, Kevin A. Boulais
  • Multi-wavelength semiconductor image sensor and method of manufacturing the same
    Patent number: 6465860
    Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.7Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keitaro Shigenaka, Fumio Nakata
  • Pendeoepitaxial gallium nitride semiconductor layers on silicon carbide substrates
    Patent number: 6462355
    Abstract: An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: October 8, 2002
    Assignee: North Carolina State University
    Inventors: Kevin J. Linthicum, Thomas Gehrke, Darren B. Thomson, Eric P. Carlson, Pradeep Rajagopal, Robert F. Davis
  • Isolation of memory cells in cross point arrays
    Patent number: 6462388
    Abstract: A memory array includes memory cells located at cross points of first and second conductors. The memory cells are compound structures that are capable of storing data, and of isolating the memory cells from sneak path currents. The memory cells include tunnel gate surface effect transistors having non-uniform gate oxides. The gate oxides are supported on pillar diode structures. A memory cell stores a binary state in a tunnel junction of the gate oxide. In addition, a control gate of the transistor disconnects the tunnel junction from sidewalls of the pillar, preventing current flow. The control gate therefore prevents sneak path currents through the memory cell. The isolation features in the memory cells do not require space on the substrate, allowing for a high array density. In addition, the memory cells have a low forward voltage drop, improving the readability of the memory array.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: October 8, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Frederick A. Perner
  • Method for fabricating a small area of contact between electrodes
    Patent number: 6462353
    Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: October 8, 2002
    Assignee: Micron Technology Inc.
    Inventor: Brent Gilgen
  • Semiconductor position sensor
    Patent number: 6459109
    Abstract: A semiconductor position sensor functions as a PSD or as a two-part split PD or the like, based on control of disconnection/connection of basic, electroconductive strips by controlling a voltage of gate electrode. This semiconductor position sensor does not require a PD separate from the PSD, whereby the device itself can be constructed in compact size. Further, since all signal light can impinge on a photosensitive area, detection sensitivity can be improved.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 1, 2002
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tatsuo Takeshita, Masayuki Sakakibara, Kouji Noda
  • Microwave semiconductor device having coplanar waveguide and micro-strip line
    Patent number: 6455880
    Abstract: A high frequency semiconductor device has a semiconductor substrate such as the semi-insulating GaAs; a first metal layer disposed above the semiconductor substrate; a first dielectric thin film disposed on the first metal layer; and a second metal layer having a second metal strip disposed on the first dielectric thin film. Here, the first metal layer has a first metal strip, first and second ground metal plates sandwiching the first metal strip. And the first dielectric thin film is not disposed uniformly on the surface of the first ground metal plate so that the dielectric structure on the first metal strip differs from the dielectric structure under the second metal strip. The CPW is constituted by the first metal strip, the first and second ground metal plates, and the TFMSL is constituted by the second metal strip and the first ground metal plate.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: September 24, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Ono, Yuji Iseki, Keiichi Yamaguchi, Junko Onomura, Eiji Takagi
  • Dual-line type charge transfer device
    Patent number: 6441409
    Abstract: A charge transfer device which comprises vertical charge transfer devices which transfer charges in the vertical direction, first and second horizontal charge transfer devices which transfer the charges from the vertical charge transfer devices in the horizontal direction, and a shift gate which controls the charges from the vertical charge transfer devices to be supplied to one the first horizontal charge device or the second horizontal charge transfer device, wherein the first. horizontal charge transfer device is a semiconductor region between the vertical charge transfer devices and the second horizontal charge transfer device and includes highly-doped regions having tapered portions whose one ends near the second horizontal charge transfer device are broader than another ends near the vertical charge transfer devices.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: August 27, 2002
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Yong Gwan Kim
  • Solid-state image sensor having a substrate with an impurity concentration gradient
    Patent number: 6441411
    Abstract: A solid-state image sensor comprises a semiconductor substrate, a photoelectric conversion portion formed above the semiconductor substrate, and noise cancelers each formed, adjacent to the photoelectric conversion portion, on the semiconductor substrate through an insulating film, for removing noise of a signal read from the photoelectric conversion portion, wherein the semiconductor substrate has a conductive type opposite to a conductive type of a charge of the signal, and has a first region where concentration of impurities for determining the conductive type is high and a second region where concentration of the impurities on the first region is low.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: August 27, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nozaki, Hirofumi Yamashita, Hisanori Ihara, Tetsuya Yamaguchi, Ikuko Inoue
  • Acceleration sensor and method of manufacturing the same
    Patent number: 6441450
    Abstract: Providing an acceleration sensor in which a base portion and a cap portion are bonded to each other and a sensor portion is sealed off between these two, and which has an improved bonding strength between the base portion and the cap portion. A sensor portion and a frame portion surrounding a periphery of the sensor portion are disposed on a semiconductor substrate. A base portion is comprised, where a diffusion preventing layer and a non-doped polycrystalline silicon layer are stacked one atop the other on the frame portion. A cap portion is comprised, where a nickel layer is formed on a base unit. The non-doped polycrystalline silicon layer of the base portion and the nickel layer of the cap portion are bonded to each other by eutectic bonding.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: August 27, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited, Ryoden Semiconductor System Engineering Corporation
    Inventors: Yasuo Yamaguchi, Kunihiro Nakamura, Shiro Yamasaki, Teruya Fukaura
  • Image sensor structure and manufacturing process therefor
    Patent number: 6437370
    Abstract: The present invention is directed to an image sensor comprising a thin film transistor on a transparent substrate, the first interlayer film covering the thin film transistor, a photodiode as a photodetector on the first interlayer film and the second interlayer film on the photodiode and the first interlayer film, where the first and the second interlayer films are made of different materials and at least a contact hole to the element consisting of polysilicon in the thin film transistor is formed after removing the second interlayer film around the area where contact holes are to be formed.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: August 20, 2002
    Assignee: NEC Corporation
    Inventor: Fumihiko Matsuno
  • N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same
    Patent number: 6433397
    Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Rama Divakaruni, Louis Lu-Chen Hsu, Yujun Li
  • Method and apparatus for cylindrical semiconductor diodes
    Patent number: 6433370
    Abstract: Semiconductor diodes are diode connected cylindrical junction field effect devices having one diode terminal as the common connection between a top gate, a back gate and a first channel terminal of the cylindrical junction field effect devices. The second diode terminal of the semiconductor diodes being the second channel terminal of the diode connected cylindrical junction field effect devices. The method of processing the cylindrical junction field effect devices provide very short channels, shallow diffused regions and trench terminated junctions at the edges of the active device for low forward voltage turn-on and high reverse bias breakdown. The trench terminated junctions spread the breakdown energy over the entire active device region rather than just device edges.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: August 13, 2002
    Assignee: VRAM Technologies, LLC
    Inventor: Richard A. Metzler
  • Active pixel sensor with inter-pixel function sharing
    Patent number: 6423994
    Abstract: An image sensor having a plurality of pixels comprising a semiconductor material of a first conductivity type with at least two adjacent pixels, each of the pixels has a photodetector formed within the substrate and an electrical function that is shared between the adjacent pixels integrated within the adjacent pixels. The electrical function can be: a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion, a reset drain, a lateral overflow gate, an overflow drain or an amplifier, that is shared between multiple pixels resulting in a saving of space.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: July 23, 2002
    Assignee: Eastman Kodak Company
    Inventor: Robert M. Guidash
  • Memory device having a floating gate
    Patent number: 6424008
    Abstract: A semiconductor memory device including a first memory having a first floating gate formed over a semiconductor substrate, a first control gate formed over and insulated from the first floating gate, a first impurity region and a second impurity region formed within the semiconductor substrate, wherein the first impurity region is deeper than the second impurity region, and a second memory having a second floating gate formed over the semiconductor substrate, a second control gate formed over and insulated from the second floating gate, the first impurity region, and a third impurity region formed within said semiconductor substrate, wherein the first impurity region is deeper than said third impurity region, and a pair of wirings formed on and in electrical contact with the second and third impurity regions, respectively. In one embodiment, the pair of wirings may function as a bit line.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: July 23, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Field effect transitor having dielectrically isolated sources and drains and methods for making same
    Patent number: 6420764
    Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Six transistor SRAM cell having offset p-channel and n-channel transistors
    Patent number: 6414359
    Abstract: A 6T CMOS SRAM cell (100) that increases process margins for a given cell area The cell (100) comprises a pair of cross-coupled inverters (102, 104). Each inverter (102, 104) comprises a p-channel pull-up transistor (106, 108) and a n-channel pull-down transistor (110, 112). The p-channel pull-up transistors (106, 108) are offset in both the vertical and horizonal directions from the n-channel pull-down transistors (110, 112).
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: July 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Sudhir Madan
  • Photogate with improved short wavelength response for a CMOS imager
    Patent number: 6414342
    Abstract: A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer about 50 to 3000 Angstroms thick. The conductive layer may be a silicon layer, a layer of indium and/or tin oxide, or may be a stack having an indium and/or tin oxide layer over a silicon layer. The thin conductive layer of the photogate permits a greater amount of short wavelength light to pass through the photogate to reach the photosite in the substrate, and thereby increases the quantum efficiency of the photosensor for short wavelengths of light.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: July 2, 2002
    Assignee: Micron Technology Inc.
    Inventor: Howard E. Rhodes
  • Method of programmability and an architecture for cold sparing of CMOS arrays
    Patent number: 6414360
    Abstract: A P-channel transistor is disclosed having P+ source and drain regions formed in a N− well, which is formed in a P− substrate. A third P+ region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a CMOS “push-pull” output buffer circuit, the P+ well tie prevents undesired current flow from the bus back to the positive voltage supply. This prevents potential damage to the power supply plane and any additional components connected thereto. In another aspect, the N− well has formed therein both a P+ and N+ well tie. Additional switch circuitry is provided which allows for upper level programmability or selection of either one or both of the two well ties, depending upon the ultimate circuit configuration.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: July 2, 2002
    Assignee: Aeroflex UTMC Microelectronic Systems, Inc.
    Inventor: Harry N. Gardner
  • Solid-state image sensor of a MOS structure
    Patent number: 6403998
    Abstract: In a MOS type solid-state image sensor having an image pickup area formed at a semiconductor substrate and comprising a two-dimensional array of row and column unit cells including a photoelectric conversion section and signal scanning circuit, a first p well area is provided in a surface portion of an n type silicon substrate and a second p well area is selectively provided in the surface portion of the first p well area and is higher in p type impurity concentration than the first p well area. In the image pickup area, the photoelectric conversion section is formed in the first p well area and the signal scanning circuit section is formed in the second p well area.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: June 11, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ikuko Inoue