Abstract: A heterojunction bipolar transistor (HBT), having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The collector layer formed from InGaAs, and the collector layer being doped n-type. The emitter layer formed from InP, and the emitter layer being doped n-type. The base layer formed of indium gallium arsenide (InGaAs) and grown by MOCVD, the base layer being tensile strained and graded, and the base layer being doped p-type with carbon. A lattice mismatch, for at least a portion of the base layer, between the substrate and the base material is greater than 0.2%.

Abstract: A solid-state image sensor compatible with a CMOS manufacturing process outputs the variation of the electric potential according to the number of accumulated electrons of a photoelectric conversion part, however, if the parasitic capacity of the photoelectric conversion part is C and the output voltage is V, V=Q/C and the solid-state image sensor has a defect that when the area of the photoelectric conversion part is simply increased to enhance the sensitivity, the parasitic capacity C is increased in proportion and the variation V of the electric potential by signal charges cannot be increased to an expected degree.

Abstract: A solid state image sensor is provided with a primary first-conductivity-type semiconductive region which serves as a charge storage region of a photo-sensing area and a secondary first-conductivity-type semiconductive region for enlarging a charge collecting region of the photo-sensing area.

Abstract: There is provided a solid state imaging device which has been improved in-to-noise characteristics and sensitivity and which can be fabricated with high yield. In a solid state imaging device (1) including a light receiving portion (2) having an opening portion (7) formed as a pixel, a low reflection (9) film is formed on the opening portion of the light receiving portion. Light beams (LF) incident upon the light receiving portion is a plurality of colors selected for respective pixels. The low reflection film has a film thickness or a refractive index selected for each pixel so as to correspond to a color of the light (LF) incident upon the light receiving portion (2).

Abstract: A method for designing an avalanche photodiode for high bit rate or high speed applications is disclosed. The photodiode is made up of a multiplication layer of a first semiconductor material, an absorption layer of a second semiconductor material and a field control layer of a third semiconductor material having. The field control layer has a moderate doping of a first type dopant and is intermediate between the multiplication and absorption layers. A central region of the multiplication layer is diffused with a second type dopant which results in a diffused region having a greater thickness in the center than in the periphery of the diffused region.

Abstract: A superjunction device has a large number of symmetrically located vertical circular wells in a high resistivity silicon substrate. A plurality of alternate opposite conductivity N and P stripes or nodes are formed along the length of the walls of each of the wells. Each of the nodes faces an opposite concentration type node in an adjacent well. A DMOS gate structure is connected to the tops of the N stripes. The nodes have a depth and concentration to cause full depletion of all nodes during reverse bias. Current flows through the relatively low resistance N stripes when its gate is turned on. A conventional termination such as a diffused ring or rings can surround the active area of all cells and is formed in the high resistivity substrate.

Abstract: By providing a semiconductor device including a charge transfer channel to one end of which electric charges supplied from a charge supply unit are input, and which includes a plurality of branching regions at an intermediate portion, a plurality of gate electrodes provided on the corresponding branching regions of the charge transfer channel via insulating films, an input-signal supply unit for supplying each of the gate electrodes with an input signal, a transfer electrode, provided on the charge transfer channel via a gate insulating film, for performing control so that the electric charges are transferred in a predetermined direction within the charge transfer channel, a conversion unit for coverting the transferred electric charges into a voltage, and a sense amplifier to which an output signal from the conversion unit is input, and by providing a semiconductor circuit which includes such a device, it is possible to reduce the scale of circuitry, increase the calculation speed, and reduce electric power

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL<0.063) and the gate delay (CV/I) is reduced to 2.4 ps.

Abstract: A solid state image pickup device is provided, that improves the transfer efficiency of charges in the horizontal charge transfer path by implementing a selectively arranged matrix of semiconductor layers with differing conductivity type, impurity concentration and orientation. Further, the solid state image pickup device prevents the lowering of the transfer efficiency of charges transferred from the vertical charge transfer path to the horizontal charge transfer path.

Abstract: An apparatus and method is presented for a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die. The use of a sacrificial insulating layer, an etch-stop insulating layer, and insulating spacers surrounding the bit line contact plug permits wet etching of the sacrificial layer to enable double-sided capacitors to be formed close together. In the resulting structure, only the bit line contact plug and insulating sidewall spacers separates adjacent capacitors and hence DRAM cells can be more tightly packed on the circuit die. Another aspect of the invention is improved alignment tolerance of the bit line contact plug.

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

Abstract: The invention relates to a method of manufacturing a double heterojunction bipolar transistor (1) comprising successively at least one sub-collector layer, a collector layer, a base layer and a metallic layer (10) deposited on the said base layer; the said metallic layer (10) being extended towards a contact pad (110) of the base by an underetched metallic “air bridge” (100), characterized in that producing the said “air bridge” (100) includes the following steps: effecting a first localized etching under the said bridge, this first etching being selective so as to etch the sub-collector layer laterally; and effecting a second localized etching under the said bridge, this second etching being selective so as to vertically etch at least the collector layer.

Abstract: In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate's surface beneath the field insulation film, field limiting rings (FLRS) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape.

Abstract: According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

Abstract: The present invention relates to a pinned photodiode for an image sensor and a method for manufacturing the same; and, more particularly, to a pinned photodiode of an image sensor fabricated by CMOS processes and a manufacturing method thereof. The pinned photodiode, according to an embodiment of the present invention, comprises: a semiconductor layer of a first conductivity type; and at least two first doping regions of a second conductivity type alternately formed in the semiconductor layer and connected to each other at edges thereof so that the first doping regions have the same potential, wherein a plurality of PN junctions is formed in the semiconductor layer and the PN junctions improve a capturing capacity of photoelectric charges generated in the photodiode.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A charge coupled device including: a substrate; a semiconductor layer overlying the substrate; a semiconductor layer overlying the semiconductor layer; a charge storage layer existing on the semiconductor layer and sandwiched by a pair of isolation regions; an impurity region between the semiconductor layer and the charge storage layer; a dielectric film overlying the charge storage layer and the isolation regions, and an electrode formed by a conductive film. In accordance with the present invention, the increase of the amount of the charge storage and of the higher photosensitivity can be simultaneously satisfied. The fluctuation of the characteristics of the charge coupled device in accordance with the present invention is smaller than that of the conventional charge coupled device. Further, the method of the fabrication is less complicated than that for the conventional charge coupled device.

Abstract: The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 Å thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. In a preferred embodiment, the preferably high recombination rate buffer layer is an LT GaAs or GaAs:Er buffer layer.