Abstract: A polygonal nut 5 for receiving a clamping bolt 7 is securely inserted in a nut insertion hole 6 which is formed in the thin portion 1a of the resin case 1, and the polygonal nut is engaged with an inner surface 6a of the nut insertion hole 6. The inner surface 6a of the nut insertion hole 6 has a round-shaped notch concave portion 6b formed at a position confronting to a corresponding corner portion 5b of the polygonal nut 5 so that the corner portion 5b of the polygonal nut 5 is not in contact with a resin case member to thereby prevent the resin case from being cracked.

Abstract: A liquid crystal device comprising a pair of substrates 3a and 3b which are bonded together by a sealing material 2, and a plurality of electrodes 9a and 9b which are formed on the inside surfaces of these substrates. The electrodes 9a have wiring lines 17a and 17b which pass through the sealing material 2 and extend to a substrate projecting part 4a, and dummy patterns 19a which pass through the sealing material 2 at the side opposite to the wiring lines 17a and 17b; dummy patterns 19a are formed with a width which is smaller than the width of the electrodes 9a inside the region surrounded by the sealing material 2; preferably, they are formed with the same width as the wiring lines 17a.

Abstract: A semiconductor device includes a SiC substrate and an ohmic electrode, a semiconductor member including a SiC member and a SiGe member being formed between the SiC substrate and the ohmic electrode, wherein the semiconductor member is composed of a SiGe member formed on a SiC member, and the ohmic electrode is formed on the SiGe member, whereby the ohmic electrode with a low resistance can be formed on the SiC substrate without conducting a heat treatment at a high temperature.

Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.

Abstract: A two-step chlorination/alkylation technique used to introduce alkyl groups, —CnH2n+1 (n=1-6), functionally onto single-crystal, (111)-oriented, n-type Si surfaces. H-terminated Si photoanodes were unstable under illumination in contact with an aqueous 0.35 M K4Fe(CN)6-0.05 MK3Fe(CN)6 electrolyte. Such electrodes displayed low open-circuit voltages and exhibited a pronounced time-dependent deterioration in their current density vs potential characteristics due to anodic oxidation. In contrast, Si surfaces functionalized with —CH3 and —C2H5 groups displayed significant improvements in stability while displaying excellent electrochemical properties when used as photoelectrodes in the aqueous Fe(CN)63−/4− electrolyte.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: An asymmetrical polysilicon thin film transistor is formed above a gate electrode on a semiconductor substrate. The transistor is separated from the gate electrode by a gate oxide layer, and includes a channel region immediately above the gate electrode. Highly doped source/drain regions are formed within the polysilicon on either side of the channel region. On the drain side of the channel only, a lightly doped drain region is formed between the channel region and the highly doped drain region. The highly doped source region is immediately adjacent the channel region.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract: A pinned photodiode is operated without a transfer gate. This is done by forming a pinned photodiode which has a selective connection to the substrate. When the connection is turned on, the photodiode is pinned to the substrate, and kept at a specified potential. When the connection is off, the photodiode is disconnected from the substrate and hence floats. In this way, the area above the photoreceptor can be used both for a reception area and for a charge transfer area.

Abstract: In a semiconductor memory device including memory cells MC with MOS type structure comprising gate electrodes G and source regions S and drain regions D formed in both sides of the gate electrodes G formed on a semiconductor substrate, the source regions S comprise metal silicide layers 121 only in the source contact regions. Even if projected and recessed parts exist in the surface of the source regions S, since the metal silicide layers 121 are not formed on the projected and recessed parts, the metal silicide layers 121 are not disconnected in the projected and recessed parts, and the metal for forming the metal silicide layers 121 does not absorb silicon atom in the source regions S.

Abstract: A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a semiconductor layer at least a part of which is formed on the first insulating film; a second insulating film comprising a non-doped silicon oxide film and formed on the semiconductor layer; a third insulating film comprising a silicon oxide film containing at least phosphorus formed on the second insulating film; and a fourth insulating film comprising a non-doped silicon oxide film formed on the third insulating film.

Abstract: In a thin-film transistor to be used in an active matrix liquid crystal display device, each of a gate signal line, a source signal line, and a drain extraction electrode has a three-layer structure. Specifically, each of these members is made up of a lower layer made of a titanium film, an intermediate layer made of an aluminum film, and an upper layer made of a titanium film containing nitrogen. Since the respective upper layers, in contact with a gate insulating film or an interlayer insulating film made of a silicon nitride film, are made of titanium films containing nitrogen, they have superior adhesion to the silicon nitride film. Consequently, film peeling, etc. during the manufacturing process can be suppressed. Further, providing the titanium film beneath the aluminum film contributes to reduction of the resistance of the aluminum film.

Abstract: A semiconductor device is provided which is capable of reducing the number of masking processes in forming contact holes. The semiconductor device comprises a semiconductor substrate (1), a gate structure (9), a stopper film (11), an interlayer insulation film (12), a contact hole (17) extending from the upper surface (13) of the interlayer insulation film (12) to the semiconductor substrate (1), a metal material (18) buried in the contact hole (17), a first metal wiring layer (19), an interlayer insulation film (20), a contact hole (23) extending from the upper surface (21) of the interlayer insulation film (20) to the first metal wiring layer (19), and a contact hole (24) extending from the upper surface (21) of the interlayer insulation film (20) to a gate electrode (7) of the gate structure (9). The contact hole (24) is formed at the same time as the contact hole (23).

Abstract: In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are laid out equally in the chip, and SRAMs and are arranged equally in the vicinity of each of anode driver regions so that drawing of wiring becomes easy and size of the chip is miniaturized.

Abstract: A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.

Abstract: The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.