Patents Examined by George Eckert
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Patent number: 6844588Abstract: A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. Each column of the array is located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials to each column, with isolation of results for each column. In one embodiment, the memory cells are devoid of floating gate devices and use a non-conductive charge storage layer to store charges. In another embodiment, the memory cells store charges in nanocrystals.Type: GrantFiled: December 19, 2001Date of Patent: January 18, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Craig A. Cavins, Ko-Min Chang
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Patent number: 6844245Abstract: A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarized and a passivation layer is deposited. This passivation layer can be thinned over a fuse portion of the copper. The fuse portion can then be laser fused to form a crater in an area surrounding a blown copper fuse. Exposed portions of the pure copper can then be self-passivated by annealing the device.Type: GrantFiled: December 23, 2003Date of Patent: January 18, 2005Assignee: Infineon Technologies AGInventor: Hans-Joachim Barth
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Patent number: 6838722Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.Type: GrantFiled: March 22, 2002Date of Patent: January 4, 2005Assignee: Siliconix IncorporatedInventors: Anup Bhalla, Dorman Pitzer, Jacek Korec, Xiaorong Shi, Sik Lui
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Patent number: 6835629Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.Type: GrantFiled: January 23, 2003Date of Patent: December 28, 2004Assignee: STMicroelectronics S.r.l.Inventor: Piero Fallica
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Patent number: 6833883Abstract: An array substrate for a reflective liquid crystal display device, including a gate line and a data line defining a pixel region by crossing each other; a switching element at a crossing portion of the gate line and the data line; a first passivation layer covering the switching element and the data line; and formed of an inorganic insulating material; a reflective electrode on the first passivation layer, and connected to the switching element; and a second passivation layer on the reflective electrode. The second passivation layer being formed of an organic insulating material.Type: GrantFiled: December 28, 2001Date of Patent: December 21, 2004Assignee: LG. Philips LCD Co., Ltd.Inventors: June-Ho Park, Jae-Sik Choi
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Patent number: 6831370Abstract: A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower dielectric constant and therefore reduces the capacitive coupling between electrical interconnects on adjacent chips. The foamed insulating material also has higher ductility and lower thermal coefficient of expansion than conventional oxide insulators so as to reduce the occurrence of stress induced cracking in circuitry.Type: GrantFiled: July 19, 2001Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 6815774Abstract: A dielectrically separated wafer and a fabrication method of the same are provided according to the first, second and third embodiments of the present invention. According to the first embodiment, it becomes possible to expand the device fabrication surface area of the dielectrically separated silicon islands by laminating a low concentration impurity layer including a dopant of the same conductivity on a high concentration impurity layer formed on the bottom of the island. According to the second embodiment, a dielectrically separated wafer and a fabrication method for the same which can grow a polysilicon layer without producing voids in the dielectrically separating oxide layer is provided by forming a seed polysilicon layer at low temperature and under low pressure and by forming, on the seed polysilicon layer, a high temperature polysilicon layer 16.Type: GrantFiled: October 18, 1999Date of Patent: November 9, 2004Assignee: Mitsubishi Materials Silicon CorporationInventors: Hiroyuki Oi, Kazuya Sato, Hiroshi Shimamura
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Patent number: 6812575Abstract: In a semiconductor device with a plurality of semiconductor chips stacked on a substrate, a wiring layer disposed so as to be sandwiched between the semiconductor chips, and a plurality of bonding pads, for connecting a bonding wire, provided on the wiring layer, are provided.Type: GrantFiled: August 28, 2001Date of Patent: November 2, 2004Assignee: NEC CorporationInventor: Koji Furusawa
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Patent number: 6808976Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.Type: GrantFiled: August 31, 2000Date of Patent: October 26, 2004Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 6803290Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.Type: GrantFiled: August 31, 2000Date of Patent: October 12, 2004Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 6798020Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.Type: GrantFiled: February 10, 2003Date of Patent: September 28, 2004Assignee: Power Integrations, Inc.Inventors: Donald Ray Disney, Mohamed Darwish
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Patent number: 6791658Abstract: Two electric fields that are directed to respective directions rectangular relative to each other are selectively applied to polymer dispersed liquid crystal by means of electrodes arranged to sandwich the polymer dispersed liquid crystal and electrodes arranged along a substrate to uniformly orient the liquid crystal in either of the directions. While conventional polymer dispersed liquid crystal is adapted to utilize scatter of light in a randomly oriented state, the polymer dispersed liquid crystal of this invention is adapted to utilize a uniformly oriented state to improve the efficiency of scattering light. The present invention is also applicable to devices where polymer dispersed liquid crystal has a memory property.Type: GrantFiled: September 12, 2001Date of Patent: September 14, 2004Assignee: Canon Kabushiki KaishaInventors: Tomoko Maruyama, Yoshinori Uno
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Patent number: 6790712Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.Type: GrantFiled: August 9, 2002Date of Patent: September 14, 2004Assignee: United Test Center, Inc.Inventor: Jin-Chuan Bai
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Patent number: 6791124Abstract: A sequential mesa type avalanche photodiode (APD) comprises a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.Type: GrantFiled: September 9, 2002Date of Patent: September 14, 2004Assignee: Anritsu CorporationInventors: Jun Hiraoka, Kazuo Mizuno, Yuichi Sasaki
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Patent number: 6790713Abstract: A semiconductor device having a thyristor is manufactured and arranged in a manner that reduces or eliminates difficulties commonly experienced in the formation and implementation of such devices. According to an example embodiment of the present invention, a thyristor (e.g., a thin capacitively-coupled thyristor) is formed having some or all of the body of the thyristor formed inlayed in a semiconductor device substrate. A trench is provided in the substrate, and a semiconductor material is formed in the trench. One or more layers of material are formed in the trench and used to form a portion of a body of the thyristor. The thyristor is formed having adjacent regions of different polarity, wherein at least one of the adjacent regions includes a portion of the semiconductor material and at least one of the adjacent regions includes a portion of the substrate.Type: GrantFiled: September 9, 2002Date of Patent: September 14, 2004Assignee: T-Ram, Inc.Inventor: Andrew Horch
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Patent number: 6787870Abstract: A semiconductor component with an integrated circuit has a cooling body as a heat sink and a temperature sensor thermally connected thereto, whose resistance is dependent on temperature. The temperature sensor contains a thin film measuring resistor, which is applied to an electrically insulating surface of a foil-like substrate, and the total thickness of the temperature sensor lies in a range of about 10 &mgr;m to 100 &mgr;m. The thin film measuring resistor is formed as a planar component, with the temperature sensor being arranged between the integrated circuit and the cooling body. The thin film measuring resistor is provided on one side with a thermal coupling layer bordering on the cooling body, while on the other side the resistor has a substrate bordering on a heat distributor, which at least partially surrounds the integrated circuit.Type: GrantFiled: May 23, 2003Date of Patent: September 7, 2004Assignee: Heraeus Sensor Technology GmbHInventors: Karl-Heinz Wienand, Karlheinz Ullrich
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Patent number: 6784457Abstract: There is a problem in that, in a liquid crystal display panel in which a color filter is formed on an opposing substrate, it is necessary to assemble an element substrate and the opposing substrate by extremely high precision position alignment, and when this precision is low, the aperture ratio decreases and the display becomes darker. With the present invention, red color filters (R) are formed on driving circuits (402, 403), peripheral circuits, and a color filter (405d) for protecting a pixel TFT portion (407) is formed for each pixel.Type: GrantFiled: December 12, 2000Date of Patent: August 31, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara
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Patent number: 6781238Abstract: A semiconductor device having a plurality of wiring layers in a multi-layered structure, includes an inner area at a surface and a pad area surrounding the inner area therein, and further includes a device fabricated below the pad area. The device is comprised of at least one of a bypass capacitor, a protection device, and an input/output device. For instance, the bypass capacitor is comprised of metal wire layers arranged below the pad area.Type: GrantFiled: April 3, 2001Date of Patent: August 24, 2004Assignee: NEC CorporationInventor: Makoto Nonaka
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Patent number: 6777793Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is deposited in a packaging mold, and the packaging mold comprises a plurality of injection pins for pushing the packaging substrate out of the packaging mold. A first copper-mesh layer and a second copper-mesh layer of the packaging substrate are electrically connected to each other via position pins. A bottom side of the packaging substrate comprises a plurality of recesses in positions corresponding to positions of the injection pins. The recesses pass the second copper-mesh layer to electrically connect the injection pins to the second copper-mesh layer, and static electric charges are conducted to the injection pins via the second copper-mesh layer and away from the packaging substrate. It prevents dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.Type: GrantFiled: November 7, 2002Date of Patent: August 17, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Meng-Tsang Lee, Kuang-Lin Lo
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Patent number: 6773993Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.Type: GrantFiled: June 15, 2001Date of Patent: August 10, 2004Assignee: Nanya Technology CorporationInventors: Chi-Hui Lin, Chung-Lin Huang, Cheng-Chih Huang