Patents Examined by Guerrier Merant
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Patent number: 11410743Abstract: A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range.Type: GrantFiled: December 4, 2020Date of Patent: August 9, 2022Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Zhengang Chen
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Patent number: 11397639Abstract: A method for operating a memory system includes: performing a read operation in response to a first tag; performing a read operation in response to a second tag; performing a defense code operation corresponding to the first tag; performing an error correction code (KC) operation on data output through the defense code operation corresponding to the first tag; and performing a defense code operation corresponding to the second tag, wherein the read operation in response to the second tag is started before the ECC operation corresponding to the first tag is completed, and wherein the defense code operation corresponding to the second tag is performed using a result of the defense code operation corresponding to the first tag.Type: GrantFiled: July 13, 2020Date of Patent: July 26, 2022Assignee: SK hynix Inc.Inventors: Seon Ju Lee, Min Hwan Moon
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Patent number: 11398287Abstract: Technology is disclosed herein for a semiconductor die, and controlling operation of the semiconductor die. In some aspects, a semiconductor die is configured to test an I/O circuit on the semiconductor die. The semiconductor die has an input circuit that compares a voltage signal at one of a first input or a second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The first input may be connected to an I/O contact. During a normal mode a control circuit on the die provides a reference voltage to second input. During a test mode, the control circuit internally loops back a test signal from an output circuit to the second input of the input circuit. Thus, the test signal avoids the I/O contact.Type: GrantFiled: March 24, 2020Date of Patent: July 26, 2022Assignee: SanDisk Technologies LLCInventors: Tianyu Tang, Venkatesh Ramachandra
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Patent number: 11386003Abstract: Methods, systems, and devices for forwarding a code word address are described. A memory subsystem, for example, may configure a code word including user data as a forwarded code word when the code word becomes unreliable or invalid close to or beyond an error recovery capability of the memory subsystem. The memory subsystem may configure the forwarded code word using a forwarded code word format and structure, which may include a bit field in the forwarded code word to indicate a code word condition and to store a quantity of duplicates of a forwarding address. When the memory subsystem receives a code word, the memory system may determine the code word as a forwarded code word such that the memory system may determine a forwarding address (e.g., from the code word). The memory subsystem may then use the forwarding address to access user data.Type: GrantFiled: October 15, 2020Date of Patent: July 12, 2022Assignee: Micron Technology, Inc.Inventor: Joseph Thomas Pawlowski
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Patent number: 11385285Abstract: An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.Type: GrantFiled: October 14, 2020Date of Patent: July 12, 2022Assignee: Advantest CorporationInventors: Olaf Pöppe, Klaus-Dieter Hilliges
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Patent number: 11381256Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.Type: GrantFiled: September 15, 2020Date of Patent: July 5, 2022Assignee: Electronics and Telecommunications Research InstituteInventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
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Patent number: 11367497Abstract: An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.Type: GrantFiled: May 31, 2019Date of Patent: June 21, 2022Assignee: Micron Technology, Inc.Inventors: Alberto Troia, Antonino Mondello
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Patent number: 11360847Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.Type: GrantFiled: January 13, 2021Date of Patent: June 14, 2022Assignee: Dell Products L.P.Inventors: Ching-Lung Chao, Shih-Hao Wang, Zhengyu Yang
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Patent number: 11356118Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.Type: GrantFiled: April 21, 2020Date of Patent: June 7, 2022Assignee: Saturn Licensing LLCInventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
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Patent number: 11347587Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.Type: GrantFiled: May 22, 2020Date of Patent: May 31, 2022Assignee: Rambus Inc.Inventors: Michael Miller, Stephen Magee, John Eric Linstadt
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Patent number: 11349495Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.Type: GrantFiled: April 15, 2020Date of Patent: May 31, 2022Assignee: Seagate Technology LLCInventors: Naveen Kumar, Shuhei Tanakamaru, Erich Franz Haratsch
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Patent number: 11349613Abstract: Aspects of the present disclosure provide various hybrid automatic repeat request (HARQ) retransmission indication schemes used in a HARQ retransmission process. The HARQ retransmission indication can implicitly or explicitly indicate which part of a transport block (TB), code block group(s), or code block(s) is/are being retransmitted so that the receiver can associate the retransmitted TB, code block group(s), code block(s) with the correct prior reception, for example, for HARQ combining purposes.Type: GrantFiled: March 24, 2020Date of Patent: May 31, 2022Assignee: QUALCOMM IncorporatedInventors: Jay Kumar Sundararajan, Sony Akkarakaran, Jing Sun, Wanshi Chen, Hao Xu, Jing Jiang
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Patent number: 11327831Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.Type: GrantFiled: March 27, 2020Date of Patent: May 10, 2022Assignee: Rambus Inc.Inventors: Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
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Patent number: 11327834Abstract: In an information processing system including a set of data storage devices for storing data blocks arranged in respective columns on each data storage device and rows across the set of data storage devices to form at least one data stripe, and a set of parity storage devices for storing parity blocks computed via one or more parity operations based on the data blocks of the at least one data stripe, at least one of the data storage devices includes a processing device configured to: receive from the information processing system an instruction to perform at least a portion of a parity operation; perform the portion of the parity operation; and send a result of the performed portion of the parity operation to the information processing system, wherein the result is useable by the information processing system for performing another portion of the parity operation.Type: GrantFiled: March 18, 2020Date of Patent: May 10, 2022Assignee: EMC IP Holding Company LLCInventors: Zvi Schneider, Amitai Alkalay, Assaf Natanzon
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Patent number: 11321167Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.Type: GrantFiled: May 9, 2020Date of Patent: May 3, 2022Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
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Patent number: 11316533Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.Type: GrantFiled: April 21, 2020Date of Patent: April 26, 2022Assignee: Saturn Licensing LLCInventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
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Patent number: 11307252Abstract: A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.Type: GrantFiled: November 9, 2020Date of Patent: April 19, 2022Assignee: Istanbul Teknik UniversitesiInventors: Mustafa Altun, Sajjad Parvin
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Patent number: 11309912Abstract: Systems and methods are provided for reducing error in data compression and decompression when data is transmitted over low bandwidth communication links, such as satellite links. Embodiments of the present disclosure provide systems and methods for variable block size compression for gridded data, efficiently storing null values in gridded data, and eliminating growth of error in compressed time series data.Type: GrantFiled: September 30, 2020Date of Patent: April 19, 2022Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventor: John T. Sample
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Patent number: 11301321Abstract: A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.Type: GrantFiled: May 28, 2020Date of Patent: April 12, 2022Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Idan Alrod
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Patent number: 11300612Abstract: A debug support device includes: a root device extraction unit that extracts, from a sequence program that includes a circuit block including a plurality of devices, a result device on the basis of an association between a factor device that contributes to determination of a value of another device and the result device having the value determined by the factor device; a related device retrieval unit that retrieves, as a related device, each and every one of the factor device(s) that determines the value of the result device; and a display control unit that outputs group information to a display device. The group information is information on a group, associating the result device, the value of the result device, the related device, and a value of the related device.Type: GrantFiled: April 18, 2019Date of Patent: April 12, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Masaki Nishihara
