Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

Abstract: An autonomous RAID data storage device locking system includes first RAID data storage device(s) that store data included in a data stripe, and that are coupled to a second RAID data storage device. The second RAID data storage device receives a command to perform a data update operation on a subset of data included in the data stripe, and transmits a locking request to each first RAID data storage device. When the second RAID data storage device receives a locking confirmation that indicates that each first RAID data storage device is locked, it completes the data update operation on the subset of data included in the data stripe. The second RAID data storage device then transmits an unlocking request to each first RAID data storage device to cause them to unlock, and transmits a completion communication that indicates that the data update operation has been performed.

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform an error correction on data read from a memory region of the non-volatile memory, and set a value of a parameter corresponding to a number of parity bits to be added to write data to be written into the memory region based on a number of data bits corrected in the error correction of the read data in a case where the error correction is successful.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.

Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.

Abstract: A method of detecting leakage of a data qubit includes applying a first cross-resonance pulse to the data qubit, the data qubit including a first state and a second state; applying a first echo pulse to the data qubit temporally following the applied first cross-resonance pulse; applying a second cross-resonance pulse to the data qubit temporally following the applied first echo pulse, the second cross-resonance pulse being an inverted form of the first cross-resonance pulse; applying a second echo pulse to the data qubit temporally following the second cross-resonance pulse; and detecting a leakage associated with the data qubit using an ancilla qubit coupled to the data qubit based on application of the first and second cross-resonance pulses, and the first and second echo pulses.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.

Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.

Abstract: A method is provided for distance measurement that comprises performing measurements, wherein a measurement comprises sending out at least one measuring pulse and, if reflected on an object, receiving the reflected measuring pulse. Measurements are performed accounting for previous information about objects and/or open spaces within a maximum measuring range in order to varyingly measure subranges of the maximum measuring range. The method comprises defining subranges, classifying the subranges by relevance and varyingly measuring subranges, wherein relevant subranges are measured more intensively, so that more measuring pulses per spatial unit are sent out in relevant subranges. The method has a time budget, wherein the method comprises a one-time definition and/or dynamic adjustment of how the time budget is distributed among varyingly relevant subranges, wherein a first portion of the time budget is used for focus measurements, and a second portion of the time budget is used for basic measurements.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: Boundary scan test data and a command to initiate a boundary scan test are received via a universal asynchronous receiver-transmitter (UART). Based on receiving the command, a boundary scan test mode is initiated at a memory sub-system controller. A boundary scan test vector based on the boundary scan test data is synchronously streamed to a boundary scan chain. Test result data output by the scan chain is provided to a UART host via the UART.

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for detecting a number of error bits from data stored in the plurality of pages; summing the number of error bits; generating a bad word line list based on the sum of the error bits; and performing a test read operation on the plurality of pages based on the bad word line list.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.