Patents Examined by Guy J. Lamarre
-
Patent number: 11500719Abstract: To improve the reliability of a memory system, data and error correction codes associated with the data can be stored in a first memory. Parity bits calculated over data bits in the first memory can be stored in a second memory. The parity bits in the second memory can be used to recover errors that are uncorrectable by the error correction codes. The first memory can be implemented, for example, using an emerging memory technology, while the second memory can be implement using a different memory technology.Type: GrantFiled: March 31, 2020Date of Patent: November 15, 2022Assignee: Amazon Technologies, Inc.Inventors: Charan Srinivasan, Nafea Bshara
-
Patent number: 11500720Abstract: A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.Type: GrantFiled: September 21, 2020Date of Patent: November 15, 2022Assignee: SK hynix Inc.Inventor: Jeen Park
-
Patent number: 11494319Abstract: A memory device may support multiple DQ maps. Two or more of the DQ maps may support memory operations using a same input-output width. In some examples, one or more components for supporting a DQ map for a different input-output width may be used to also support one or more of the DQ maps for the same-input output width.Type: GrantFiled: August 17, 2021Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: Jaeil Kim, Suryanarayana B. Tatapudi
-
Patent number: 11496154Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.Type: GrantFiled: November 5, 2020Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Thomas Joseph Richardson, Shrinivas Kudekar
-
Patent number: 11494261Abstract: A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process.Type: GrantFiled: July 1, 2020Date of Patent: November 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Stella Achtenberg, Ran Zamir, Ofir Pele, Omer Fainzilber
-
Patent number: 11494266Abstract: A RAID storage-device-assisted parity data update system includes a first RAID primary data drive that DMA's second primary data from a host system, and XOR's it with first primary data to produce first interim parity data for a first data stripe. A second RAID primary data drive DMA's fourth primary data from the host system, and XOR's it with third primary data to produce second interim parity data for a second data stripe. A first RAID parity data drive DMAs the first interim parity data and XOR's it with first parity data to produce second parity data for the first data stripe that overwrites the first parity data. A second RAID parity data drive DMA's the second interim parity data and XOR's it with third parity data to produce fourth parity data for the second data stripe that overwrites the third parity data.Type: GrantFiled: May 6, 2021Date of Patent: November 8, 2022Assignee: Dell Products L.P.Inventors: Gary Benedict Kotzur, William Emmett Lynn
-
Patent number: 11494259Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.Type: GrantFiled: December 11, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Norio Hattori
-
Patent number: 11495296Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. To improve the accuracy of recovering the encoded foggy phase data, techniques are presented to calibrate the voltage levels used in sensing the foggy state distributions.Type: GrantFiled: February 9, 2021Date of Patent: November 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Idan Alrod, Eran Sharon, Sergey Anatolievich Gorobets, Jack Frayer, Tien-Chien Kuo, Alexander Bazarsky
-
Patent number: 11487617Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.Type: GrantFiled: November 30, 2020Date of Patent: November 1, 2022Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent S. Haukness, Lawrence Lai
-
Patent number: 11467901Abstract: Devices and techniques for disposable parity are described herein. First and second portions of data can be obtained, and respective parity values stored in adjacent memory locations. An entry mapping the respective parity values to the first and second portions of data is updated when the parity values are stored. If an error occurs when writing a portion of data, the mapping entry is used to retrieve the parity data to correct the error. Otherwise, the parity data is discarded.Type: GrantFiled: September 3, 2020Date of Patent: October 11, 2022Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
-
Patent number: 11469776Abstract: A low density parity check (LDPC) channel encoding method for use in a wireless communications system includes a communication device encoding an input bit sequence by using a LDPC matrix to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The encoding method can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.Type: GrantFiled: August 31, 2020Date of Patent: October 11, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Liang Ma, Chen Zheng, Xiaojian Liu, Yuejun Wei, Xin Zeng
-
Patent number: 11467903Abstract: Embodiments of the present disclosure provide a memory system and an operating method thereof. A memory system includes a memory device and a memory controller. The memory controller is configured to create a bad memory area replacement table including state information of a bad memory area among a plurality of memory areas, add the state information of one or more runtime bad memory areas to the bad memory area replacement table when one or more runtime bad memory areas occur, and remap, based on the bad memory area replacement table, a bad sub-area included in a target memory area to a normal sub-area included in one of remaining bad memory areas other than the target bad memory area among the bad memory areas added to the bad memory area replacement table.Type: GrantFiled: April 15, 2021Date of Patent: October 11, 2022Assignee: SK hynix Inc.Inventor: In Jong Jang
-
Patent number: 11467938Abstract: A controller optimizes read retry thresholds for a memory device using one or more previous reads and a condition. The controller determines a read level table based on a condition indicative of a state of the memory device and selects an entry among multiple entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines fail bits for data associated with multiple read operations on the cells using multiple read retry thresholds; and determines an order of the multiple read retry thresholds based on the fail bits determination.Type: GrantFiled: September 21, 2020Date of Patent: October 11, 2022Assignee: SK hynix Inc.Inventors: Meysam Asadi, Aman Bhatia, Fan Zhang
-
Patent number: 11455208Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.Type: GrantFiled: February 9, 2021Date of Patent: September 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Omer Fainzilber, David Avraham, Eran Sharon
-
Patent number: 11436086Abstract: A RAID storage-device-assisted deferred parity data update system includes a RAID primary data drive that retrieves second primary data via a DMA operation from host system, and XOR's it with first primary data to produce first interim parity data, which causes a RAID storage controller device to provide an inconsistent parity stripe journal entry in the host system. The RAID primary data drive then retrieves third primary data via a DMA operation from the host system, XORs it with the second primary data and the first interim parity data to produce second interim parity data. A RAID parity data drive retrieves the second interim parity data via a DMA operation, and XORs it with first parity data to produce second parity data that it uses to overwrite the first parity data, which causes the RAID storage controller device to remove the inconsistent parity stripe journal entry from the host system.Type: GrantFiled: May 5, 2021Date of Patent: September 6, 2022Assignee: Dell Products L.P.Inventors: Gary Benedict Kotzur, William Emmett Lynn, Kevin Thomas Marks, Chandrashekar Nelogal, James Peter Giannoules, Austin Patrick Bolen
-
Patent number: 11436082Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.Type: GrantFiled: January 19, 2021Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Aaron P. Boehm, Scott E. Schaefer
-
Patent number: 11436081Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.Type: GrantFiled: September 11, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hanbyeul Na, Jaehun Jang, Hongrak Son
-
Patent number: 11438095Abstract: The present disclosure relates to a communication apparatus and method for supporting a forward error correction scheme in a communication system. To this end, by means of a generation mode among a plurality of generation modes (ssbg_mode #0, #1, #2), a source symbol block having a plurality of source symbols is generated by using a source packet block having a plurality of source packets, and a repair symbol block for the generated source symbol block is generated by means of a forward error correction (FEC) scheme among a plurality of FEC schemes (FEC payload ID mode 0, FEC payload ID mode 1). A first FEC scheme (FEC payload ID mode 1) is applied to generate the repair symbol block, and in response to an occurrence of a discontinuity in packet sequence numbers, a repair packet may be generated to include length repair data and a repair FEC payload identifier (ID).Type: GrantFiled: January 21, 2019Date of Patent: September 6, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunkoo Yang, Sunghee Hwang, Dongyeon Kim, Jaehyeon Bae, Youngwan So, Eric Yip
-
Patent number: 11429480Abstract: Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.Type: GrantFiled: August 31, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Bryan Hornung, David Patrick
-
Patent number: 11422884Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.Type: GrantFiled: March 24, 2021Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventor: Joseph Thomas Pawlowski
