Patents Examined by Guy J. Lamarre
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Patent number: 11573854Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.Type: GrantFiled: November 10, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CORPORATIONInventors: Gautam Bhatia, Robert Bloemer, Sunil Rao Sudhakaran
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Patent number: 11567685Abstract: A storage device may include, at least one memory device including at least a first single-level cell (SLC) region, a second SLC region, and at least one multi-level cell (MLC) region, the first SLC region having a higher data read speed than the second SLC region, and the second SLC region having a higher data read speed than the at least one MLC region, and a storage controller configured to control the migration of data among the first SLC region, the second SLC region, and the at least one MLC region.Type: GrantFiled: July 16, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwan Kim, Jea-Young Kwon, Jae-Kun Lee, Song Ho Yoon, Sil Wan Chang
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Patent number: 11562282Abstract: In methods for simulating the evolution of a real-world quantum system over time, a state-preparation sequence of quantum gates is applied to a qubit register of a quantum computer. The state-preparation sequence is configured to prepare in the qubit register an initial model state representing an initial state of the real-world quantum system. A Hamiltonian operator for the real-world quantum system is received and used in the example method. The Hamiltonian operator represents two-body potential-energy interactions in a factorized form comprising at least one Majorana operator. A time-evolution-operator sequence of quantum gates comprising a block-encoded form of the Hamiltonian operator is now applied to the qubit register of the quantum computer, yielding a changed model state that represents a time-evolved state of the real-world quantum system. A measurement operation is applied subsequently to the qubit register.Type: GrantFiled: March 5, 2020Date of Patent: January 24, 2023Assignee: Microsoft Technology Licensing, LLCInventor: Guang Hao Low
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Patent number: 11561854Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.Type: GrantFiled: September 1, 2021Date of Patent: January 24, 2023Assignee: KIOXIA CORPORATIONInventors: Noboru Okamoto, Toshikatsu Hida
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Patent number: 11562794Abstract: Provided is a storage device that performs a read operation by using a time interleaved sampling page buffer. The storage device controls a sensing point in time, when bit lines of even page buffer circuits are sensed, and a sensing point in time, when bit lines of odd page buffer circuits are sensed, with a certain time difference, and performs an Even Odd Sensing (EOS) operation in a stated order of even sensing and odd sensing. The storage device performs a two-step EOS operation and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.Type: GrantFiled: May 19, 2021Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jisu Kim, Hyunggon Kim, Sangsoo Park, Joonsuc Jang, Minseok Kim
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Patent number: 11556415Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.Type: GrantFiled: August 9, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Youngdeok Seo
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Patent number: 11557348Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.Type: GrantFiled: June 24, 2021Date of Patent: January 17, 2023Assignee: Western Digital Technologies, Inc.Inventors: Vinayak Bhat, Amiya Banerjee, Shrinidhi Kulkarni
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Patent number: 11550657Abstract: A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.Type: GrantFiled: September 1, 2021Date of Patent: January 10, 2023Assignee: APPLE INC.Inventors: Assaf Shappir, Itay Sagron
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Patent number: 11545999Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.Type: GrantFiled: February 22, 2021Date of Patent: January 3, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
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Patent number: 11544010Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.Type: GrantFiled: May 27, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Yuan He, Ming-Bo Liu
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Patent number: 11538532Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.Type: GrantFiled: March 11, 2021Date of Patent: December 27, 2022Assignee: SILICON STORAGE TECHNOLOGY, INC.Inventors: Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
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Patent number: 11537468Abstract: In some examples, a system records, in a data structure stored in a non-volatile storage, information of memory errors in respective segments of a memory. The system determines whether memory errors of a subset of the segments satisfy a criterion, and in response to determining that the memory errors of the subset of the segments satisfy the criterion, the system groups the memory errors of the subset into a partition having a size greater than a size of a segment. The system records, in the data structure, information of memory errors in the partition, and in response to a restart of the system, retrieves the data structure from the non-volatile storage for use in an operation that addresses memory errors in the system.Type: GrantFiled: December 6, 2021Date of Patent: December 27, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Debdipta Ghosh, Renganathan Meenakshisundaram
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Patent number: 11526395Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.Type: GrantFiled: November 20, 2020Date of Patent: December 13, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Wei Wang, Jiangli Zhu, Ying Yu Tai, Ning Chen, Zhengang Chen, Cheng Yuan Wu
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Patent number: 11528038Abstract: A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.Type: GrantFiled: March 24, 2021Date of Patent: December 13, 2022Assignee: Western Digital Technologies, Inc.Inventors: Dudy David Avraham, Ran Zamir, Omer Fainzilber
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Patent number: 11522559Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.Type: GrantFiled: February 22, 2021Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Ting Luo
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Patent number: 11520854Abstract: A first group of elements is element-wise multiplied with a second group of elements using a plurality of multipliers belonging to a matrix multiplication hardware unit. Results of the plurality of multipliers are added together using a hierarchical tree of adders belonging to the matrix multiplication hardware unit and a final result of the hierarchical tree of adders or any of a plurality of intermediate results of the hierarchical tree of adders is selectively provided for use in determining an output result matrix.Type: GrantFiled: October 29, 2019Date of Patent: December 6, 2022Assignee: Meta Platforms, Inc.Inventors: Yuchen Hao, Krishnakumar Narayanan Nair, Ehsan Khish Ardestani Zadeh, Rakesh Komuravelli, Abdulkadir Utku Diril, Thomas Mark Ulrich
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Patent number: 11513892Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.Type: GrantFiled: December 3, 2020Date of Patent: November 29, 2022Assignee: Arteris, Inc.Inventor: Parimal Gaikwad
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Patent number: 11513890Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command form a host device, collect environment data of the memory device, decode data associated with the read command, determine a bit error rate (BER) of the decoded data, compare the BER to a threshold, and determine whether the data associated with the read command is to be relocated. The environment data includes temperature, number of program/erase cycles, amount of grown defects, number of past relocations and time since last data relocation. The controller is further configured to dynamically adjust the threshold based on the collected environment data and an amount of time that has passed since a last relocation of the read command data.Type: GrantFiled: May 27, 2021Date of Patent: November 29, 2022Assignee: Western Digital Technologies, Inc.Inventors: Evgeny Mekhanik, Dudy David Avraham, Alexander Bazarsky
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Patent number: 11507454Abstract: Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors (“corruption patterns”). The techniques described herein identify patterns of cell errors that are likely to generate errors that cannot be corrected by an error correction code (ECC). The identification of non-correctable cells is accomplished by identifying a pattern of cell errors storing bit values that deviate from corresponding expected values. The pattern of these memory cells and various combinations of the cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If the error pattern or one or more of the combinations of erroneous cells in the pattern are not associated with patterns that are correctable via ECC, the error pattern is identified as predictive of a likely uncorrectable error.Type: GrantFiled: October 26, 2020Date of Patent: November 22, 2022Assignee: Oracle International CorporationInventor: Benjamin John Fuller
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Patent number: 11509346Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.Type: GrantFiled: July 19, 2021Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huan-Neng Chen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho, William Wu Shen