Abstract: A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask mat

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The present invention relates to a capacitor in a semiconductor device and a method for fabricating the same. The capacitor fabrication method includes the steps of: forming a lower electrode by using a thin film of (Ba,Sr)RuO3 (BSR) on a substrate provided with various device elements; forming a dielectric layer on the lower electrode by using a thin film of barium strontium titanate (BST); and forming an upper electrode on the dielectric layer.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. The semiconductor structure may include a semiconductor wafer, a semiconductor chip, and an integrated circuit. The method and structure comprises five embodiments. The first embodiment comprises heating an interior of a heating chamber that includes the oxygen/nitrogen particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen). The second embodiment comprises heating the fraction of the surface layer by a beam of radiation (e.g., laser radiation), or a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen/particles as gaseous oxygen/nitrogen-comprising molecules (e.g., molecular oxygen/nitrogen).

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: A method of joining a connection member to a capacitor foil using a staking tool having a tip of less than 0.030? (0.762 mm) in diameter. Another embodiment couples multiple connection members of a capacitor together by edge-connecting each connection member to its substantially flush neighboring connection members. In one aspect, a capacitor includes a multi-anode stack connected at a first weld by a weld joint less than 0.060? (1.524 mm) in diameter and a tab attached to one of the anodes of the multi-anode stack at a second weld. In one aspect, an exemplary method joining one or more foils using a staking tool having a tip of less than approximately 0.060? (1.524 mm) in diameter. In another aspect, a capacitor including a capacitor case having an electrolyte therein and a high formation voltage anode foil having a porous structure and located within the capacitor case.

Abstract: An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a deep hole formed in silicon oxide, and removing silicon oxide that is a support base material for the lower electrode using a solution containing hydrogen fluoride to expose the external wall of the lower electrode. According to the invention, the support base material in which a deep hole is formed is formed with an amorphous carbon film, the amorphous carbon film used as the support base material for the lower electrode is removed by dry etching after forming the lower electrode, and it is thereby possible to prevent the lower electrode from collapsing.

Abstract: A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract: A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation region and cobalt silicide films (9) are formed in the upper surfaces of the source/drain regions (4). Source/drain regions (54) are formed in the upper surface of the semiconductor substrate (1) in a logic formation region and cobalt silicide films (59) are formed in the upper surfaces of the source/drain regions (54). The cobalt silicide films (59) in the logic formation region are thicker than the cobalt silicide films (9) in the memory formation region.

Abstract: A porous aluminum anode is used in a capacitor. The porous anode is constructed by a solid freeform fabrication (SFF) process and has a plurality of pores. Each of the plurality of pores has a pore size. An electrolyte is infiltrated in the plurality of pores. An oxide layer is formed on the aluminum surface to provide a dielectric for the capacitor.

Abstract: A method of simultaneously controlling the ADI-AEI CD differences of openings having different sizes is disclosed. The openings are formed by: forming an ARC and a photoresist layer with a first and a second opening patterns of different sizes therein on a material layer, and etching the ARC and the material layer with the photoresist layer as a mask to form in the material layer a first/second opening corresponding to the first/second opening pattern, wherein the etching recipe makes the first/second opening smaller than the first/second opening pattern by a first/second size difference (?S1/?S2) and the difference between ?S1 and ?S2 is a relative size difference. The method is characterized by that an etching parameter affecting the relative size difference is set at a first value in etching the ARC and at a second value different from the first value in etching the material layer.