Patents Examined by H. Jey Tsai
  • Multiple device types including an inverted-T channel transistor and method therefor
    Patent number: 7452768
    Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: November 18, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung W. Min, James D. Burnett, Leo Mathew
  • Semiconductor device and method for fabricating the same
    Patent number: 7449379
    Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: November 11, 2008
    Assignee: Fujitsu Limited
    Inventors: Hirosato Ochimizu, Yasuyoshi Mishima
  • Methods of forming a plurality of capacitors
    Patent number: 7445990
    Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Fred D. Fishburn, James Rominger
  • Laser generated stress waves for stiction repair
    Patent number: 7435611
    Abstract: Methods and apparatus are presented to release stiction between suspended structures and the underlying surface in freestanding MEMS structures. A nanosecond rise time stress wave is launched on the backside of the Si substrate by impinging a short-duration Nd:YAG laser pulse onto a small area. The compressive stress wave propagates through the Si substrate and arrives at the site of several stiction-failed cantilevers on the front Si surface. The compressive stress wave propagates through the cantilevered structures and is reflected into a tensile wave from their free surfaces. The returning tensile wave pries off the interface, releasing the cantilevers.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: October 14, 2008
    Assignee: The Regents of the University of California
    Inventor: Vijay Gupta
  • Low leakage MIM capacitor
    Patent number: 7435641
    Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 14, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Method for manufacturing semiconductor device
    Patent number: 7432169
    Abstract: An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom of a trench formed in a P-type silicon substrate 1 is formed. An interlayer insulating film 23 is formed on the P-type silicon substrate 1. The interlayer insulating film 23 above the trench is partially etched to form a portion 30 of an opening for a collector contact. The interlayer insulating film 23 above the trench is partially etched until reaching the bottom thereof to form a residual section 32 of the opening for the collector contact. The residual section 32 of the opening for the collector contact is formed simultaneously with forming an opening 25 for an emitter contact and an opening 27 for a base contact.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 7, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Masaki Kagamihara
  • Bonding apparatus and method of bonding for a semiconductor chip
    Patent number: 7432129
    Abstract: A method of bonding and a bonding apparatus for a semiconductor chip that apply ultrasonic vibration to the semiconductor chip to bond the semiconductor chip to a substrate carry out leveling effectively at low cost and in a short time and can improve the bonding between the semiconductor chip and the substrate. In a positioning step, bumps of the semiconductor chip and pads of the substrate are positioned and placed in contact. In a leveling step, ultrasonic vibration of a first predetermined frequency is applied to the semiconductor chip to make the bumps of the semiconductor chip and the pads of a substrate rub against each other to level the bumps. In a bonding step, ultrasonic vibration of a second predetermined frequency that differs to the first predetermined frequency is applied to the semiconductor chip to bond the bumps and pads of the semiconductor chip and the substrate.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: October 7, 2008
    Assignee: Fujitsu Limited
    Inventor: Takayoshi Matsumura
  • Method for implementation of back-illuminated CMOS or CCD imagers
    Patent number: 7425460
    Abstract: A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: September 16, 2008
    Assignee: California Institute of Technology
    Inventor: Bedabrata Pain
  • Semiconductor fuses and semiconductor devices containing the same
    Patent number: 7425472
    Abstract: A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 16, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kenneth W. Marr
  • High performance system-on-chip using post passivation process
    Patent number: 7422941
    Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: September 9, 2008
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Method for processing a semiconductor wafer including back side grinding
    Patent number: 7416962
    Abstract: A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished, after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 26, 2008
    Assignee: Siltronic Corporation
    Inventors: Wesley Harrison, Roland Vandamme, David Gore
  • Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate
    Patent number: 7413952
    Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 19, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Fred D. Fishburn, James Rominger
  • Manufacturing method of a contact structure and phase change memory cell with elimination of double contacts
    Patent number: 7402455
    Abstract: The method forms a phase change memory cell with a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: July 22, 2008
    Assignees: STMicroelectronics S.r.l., Ovonyx Inc.
    Inventors: Fabio Pellizzer, Agostino Pirovano
  • Layered magnetic structures having improved surface planarity for bit material deposition
    Patent number: 7402879
    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Donald L. Yates, Joel A. Drewes
  • Formation of deep trench airgaps and related applications
    Patent number: 7400024
    Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: July 15, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventor: Eddy Kunnen
  • Top layers of metal for high performance IC's
    Patent number: 7396756
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: July 8, 2008
    Inventor: Mou-Shiung Lin
  • Formation of deep trench airgaps and related applications
    Patent number: 7396732
    Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: July 8, 2008
    Assignee: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventor: Eddy Kunnen
  • Top layers of metal for high performance IC's
    Patent number: 7385292
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: June 10, 2008
    Inventor: Mou-Shiung Lin
  • Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
    Patent number: 7384840
    Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 10, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kurt D. Beigel
  • Method for patterning a semiconductor component
    Patent number: 7378321
    Abstract: In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover layer is patterned using a photolithographic mask so that the first region is uncovered and the second region remains covered by the first cover layer. The first region is uncovered, a second cover layer is applied to the uncovered first region, and the first cover layer is removed so that the second region is uncovered. The uncovered second region is then doped.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: May 27, 2008
    Assignee: Infineon Technologies AG
    Inventor: Matthias Goldbach