Abstract: An improved method is disclosed for operating an interactive text processing system to integrate and process DP (data processing) type structured field data and WP (word or text processing) type text or string field data in the same record. The method involves displaying to the text processing system operator a menu of data type codes selectable through a keyboard for defining the types of data fields in a record. In response to operator selected field types, structured fields of fixed length and address pointers of fixed length for the string fields are established for the records. When the data is keyed in, the structured fields are concatenated with the address pointers for the string fields, and the text data, including format control codes, is stored at a system selected address on an auxiliary storage device such as a disk file.

Abstract: A method and apparatus are provided to enable interruption of list processing operations in a computer system and to enable restart from the point of interruption. A mechanism, at a predetermined point of the list processing operation, operates to recognize occurrences of interrupting events. If any such events are present, a mechanism saves the status of the list processing operation, saves the identification of the task associated with instruction executing the list processing operation and locks the list or queue. After the interrupt is handled, a mechanism restores status, and unlocks the list or queue only when the identified task is active again and the instruction which had been executing the list processing operation is again executing.

Abstract: A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. The ROS stores frequently used sequences of microinstructions and is not altered during operation. Other sequences of microinstructions which are not frequently used are stored in the reserved portion of main storage. As required, blocks of microinstructions are paged into the WCS from the main storage. One cycle of execution is saved for each machine instruction by utilizing the operation code portion directly from the instruction register of the data processing system to access a microinstruction from the first cycle control store. An array of single-bit storage devices, accessed by microinstruction addresses also utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel.

Abstract: An automated artwork generation system employs a video display and a microprocessor for verifying and editing data derived from a digitizer and utilized by a photoplotter. The system includes a data storage and retrieval apparatus in which data processed through the system is stored. The apparatus permits random access to data in a memory, and both the storing and retrieval times are minimized by establishing a direct relationship between the zone of a workpiece in which data is located and the portion of the memory in which the data is stored. Data entries in the memory are made in both a data entry file and a bulk data file. The entry file serves as an index to the bulk data file and contains abbreviated data entries and pointers identifying addresses in the bulk data file where additional related data is stored.

Abstract: A multi-source/receiver data processing system has a communication bus of at least one transfer medium. Clock signal generators have different clock frequencies with respect to each other. To prevent sources and/or receivers having a slow clock signal generator from being excluded as rightful participants from an action concerning a communication, the system determines whether said bus is "ready" for executing an action using first and second detecting means whereby it can allocate a first and a second period of time thereto, respectively. When a source/receiver determines that this second period of time has expired, the bus is indeed ready for this source/receiver and all further source/receivers which have meanwhile determined during their first period of time that the bus in ready, so the bus can be occupied by this action.

Abstract: A system comprising several peripheral microprocessors are connected to a central processor through a common bus. Each processor may access the bus using an interrupt signal. In order to avoid conflicts among processors in accessing the bus, processors are designated with decreasing priority. A processor which accesses the bus by using said interrupt signal generates at the same time an inhibit signal which prevents processors having a lower priority from emitting a said interrupt signal. In order to reduce the propagation time, a bypass network for the inhibit signal is associated with each processor and a propagation path is provided for the inhibit signal in the form of a matrix.

Abstract: A data link processor, which is basically a peripheral-controller for interfacing a main host computer system to a peripheral terminal unit, forms part of an I/O subsystem in which a base module unit houses a plurality of such peripheral-controllers (data link processors). Each base module carries a distribution control circuit card which provides a communication interface between the main host computer and the peripheral-controller. Each base module also carries a maintenance test circuit card for diagnostic testing of the peripheral-controllers. A data flow control circuit means controls direction of data transfer (a) between the host computer and peripheral-controller and (b) between the maintenance test circuit and the peripheral-controller.

Abstract: An interactive visual communications system consists of a number of similar terminals linked together by narrow band communications links. Each terminal consists of visual display apparatus having a display and a display generator, an input interactive device for providing input instructions which are converted to graphic task instructions at the terminal, a processor for processing such graphic task instructions (GTI's) to control the display system and the input interactive device. The generated graphic task instructions are directed through an interaction handler which directs the GTI's to the processor as well as to a modem for transmission over the narrow band communications link to one or more similar terminals. In addition, the interaction handler receives GTI's from the other terminals which are also processed by the processor to control the display system. The display system may include a random vector display monitor or a raster graphic display monitor.

Abstract: A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.

Abstract: Each row of video information in a display memory includes a linking character code followed by address codes representative of the address location in such display memory of a first data character of a next row of video information displayed on the CRT screen. Both row insertions and deletions may be accommodated by changing address codes under firmware control without requiring the complete rewrite of video information stored in the display memory.

Abstract: A programmable controller has a main processor and a scanner circuit in a unit that is connected through a multi-channel, multi-drop serial data link to a plurality of remotely located I/O racks. The I/O racks are adapted for connection to I/O devices connected to control a machine or process. The I/O racks each have an adapter module that communicates with a plurality of I/O modules in its rack. The adapter modules in the various racks are connected through the serial data link to a scanner circuit. Using a series of messages, the scanner circuit and the adapters couple both words of I/O status data for low density I/O modules and blocks of I/O status data for high density I/O modules. The scanner circuit also interfaces the main processor to the serial data link, coupling both conventional I/O status data and blocks of I/O status data from the main processor and organizing this data in messages for transmission over the serial data link.

Abstract: A data processing system for pre-planning the flight of an aircraft includes a plotting board arranged to supply position coordinates of selected points on a route to a processor. Other inputs to the processor provide details of known aircraft parameters such as speed, fuel load, fuel consumption and bank angle. The processor determines from these inputs for each leg of the flight variable factors such as track heading, flight time, fuel used and fuel remaining. The inputs and outputs of the processor are recorded on a suitable medium.

Abstract: This invention is concerned with an arrangement for automatically recognizing and identifying symbols and characters appearing in written form to be utilized by a connected process as input information for a high speed computer.

Abstract: A control device for an elevator system in which an operating program for the elevator can readily be changed by the addition of a read-only memory containing only instructions needed for modifying control signals computed by a standard program. To the standard computerized control device of an elevator system is added a further read-only memory and a further random access memory. The read-only memory stores programs which modify the computational results produced as a result of executing the standard programs. The computational results produced by executing the standard programs are stored in the added random access memory, there modified as a result of executing the special program stored in the added read-only memory, and then transferred to another random access memory for transfer to the devices which perform the direct control of the elevator cage of the system.

Abstract: A signal processing apparatus comprises a main unit having a frame, and a plurality of modules for processing analog signals replaceably inserted into said frame. Each of the modules has an analog-to-digital converter for the analog signals and an identification signal generator which generates a module identification signal different for each module. The main unit comprises a signal processing system and a conversion pulse clock generator. The latter one clocks each analog-to-digital converter in each module to convert analog signals to digital data. The digital data are transmitted together with the module identification signal to the signal processing system.

Abstract: A node device for use in a digital data processing and communications system of the type utilizing a bus organization for facilitating the interconnection of a large plurality of digital data processing devices (user devices) in which redundant cables are employed. The node devices are interposed between the user devices and the redundant cables to permit automatic reconfiguration of the interconnection of the user devices in the event of malfunctioning or severing of one or more of the cable sets within a minimum period of time. The node devices provide the user devices with the structure needed to detect and diagnose system problems and to effect recovery procedures. In accordance with the invention, one of the plurality of nodes functions as the Bus Controller and by sampling the remaining nodes in the system, it determines the priority with which user devices may transmit or receive data over the bus.

Abstract: Disclosed herein is a mechanism for use in a data processing system for recovering from errors detected when reading data from an array. At least two arrays, each of which may be a distinct portion of a single physical array, contain identical data. When data is written, it is written into both arrays. When data is read, it is read from one of the arrays. If an error is detected on readout, there will be a system retry and the other array will be accessed at the next read request. So long as no errors are detected, each successive read will be from the same array. An error detected on readout will cause the next read operation to access the other array.

Abstract: A terminal configuration management system manages the configuration of a microprocessor-based computer terminal which includes three types of memory elements: non-volatile read only memory, non-volatile read/write memory, and volatile random access memory, including configuration registers for storing short term configuration data that defines the configuration of the terminal. The read only memory has a block of standard configuration data, as well as configuration management processing routines stored therein which allow configuration parameters defined by the configuration data to be selectively displayed on the display screen of the terminal and to be readily modified and/or summarized through the use of specially labeled keys of a keyboard included in the terminal which correspond to the labeling used to identify the choices of configuration parameter values and groupings displayed on menu lists.

Abstract: In a computer system having a cache memory and using virtual addressing, effectiveness of the cache is improved by storing a subset of the least significant real address bits obtained by translation of a previous virtual address and by using this subset in subsequent cache addressing operations. The system functions in the following manner. In order to access a memory location in either the main memory or cache memory, a processor generates and transmits virtual address bits to the memories. The virtual address bits comprise segment, page and word address bits. The word address bits do not have to be translated, but an address translation buffer (ATB) translates the segment and page address into real address bits. A subset of the least significant bits of the latter word address bits represent the address needed for accessing the cache. In order to increase cache memory performance, the cache memory comprises a cache address unit which stores the subset of the real address bits from the ATB.

Abstract: A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e.