Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

Abstract: A command processing method and a storage controller are provided. The command processing method includes: receiving multiple read-modify-write (RMW) commands by a command processing pool of the storage controller, wherein each of the RMW commands includes a read command and a write command in pairs; locking a queue by the command processing pool and transmitting a pending first read command of the RMW commands in the command processing pool to the queue; when a second read command paired with a second write command of the RMW commands is pending, not locking the queue by the command processing pool and not transmitting the second write command to the queue; and when a third read command paired with a third write command of the RMW commands is not pending, locking the queue by the command processing pool and transmitting the third write command to the queue.

Abstract: The present disclosure describes technologies and techniques for use with a data storage controller (such as a non-volatile memory (NVM) controller) to implement self-trimming of media data. In illustrative examples, an NVM controller stores a stream of video data in a NAND storage device, such as video obtained by a security camera. The controller also stores time stamps corresponding to portions of the video data. The controller then periodically (or during idle times) scans the stored information to identify video data that has exceeded a maximum data lifetime, such as data older than one week. Such data is deemed to be old/expired and is trimmed by the controller (by, e.g., marking corresponding entries in an allocation table as deleted or invalid). In this manner, the controller performs self-trimming of older video data to, for example, limit write amplification. NVMe examples are provided.

Abstract: Systems for multi-cluster virtualized computing system management. A method for performing virtual entity replication between source computing clusters and target computing clusters commences upon establishing a virtual entity naming convention that is observed by both the source computing clusters and the target computing clusters. A snapshot from a source cluster is associated with a global snapshot ID before being transmitted to a target computing cluster. At some point in time, the source cluster will initiate acts to replicate a virtual entity to a particular data state that is associated with a particular named snapshot. A second replication protocol then commences. The second replication protocol includes exchanges that serve to determine whether or not the target computing cluster has a copy of a particular named snapshot as named by the global snapshot ID, and if so, to then initiate virtual entity replication at the target computing cluster using the named snapshot.

Abstract: A data storage device includes a data storage medium and a controller. The controller performs a boot-up sequence that includes operations that transition the data storage device from a lower operational state to a higher operational state in which the data storage device is ready to service host commands. The controller also carries out metadata updating operations independently of the boot-up sequence operations. Carrying out the metadata updating operations independently of the boot up sequence operations prevents the metadata updating operations from substantially contributing to a boot-up time.

Abstract: Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and a controller configured to load and store, during a read operation, one or more map segments selected from among the plurality of map segments. The controller may include: a compression engine configured to compress the one or more map segments and generate one or more compressed map segments and metadata corresponding thereto; a map data loading buffer configured to store the one or more compressed map segments and the metadata; and a processor configured to store the one or more compressed map segments to a random access memory (RAM) using the metadata.

Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.

Abstract: A storage system includes a storage controller that is configured to receive an input-output (IO) request and to obtain a flow control window size of the storage system. The flow control window size is dynamically adjustable by the storage controller based at least in part on an IO latency of the storage system. The storage controller is configured, in response to determining that an actual size of a portion of the IO request to be processed is greater than the flow control window size, to add an entry corresponding to the portion of the IO request to a flow control queue of the storage system with an indication that the portion of the IO request has an effective size equal to the flow control window size. The storage controller is further configured to process the entry in the flow control queue corresponding to the portion of the IO request using the actual size of the portion of the IO request.

Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.

Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.

Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

Abstract: A processing platform is configured to communicate over a network with one or more client devices, and to receive a request from a given one of the client devices for a proposed configuration of a storage system. The processing platform identifies based at least in part on the received request at least one processor to be utilized in implementing the storage system, selects a particular one of a plurality of storage system performance models based at least in part on the identified processor, computes a performance metric for the storage system utilizing the selected storage system performance model and one or more characteristics of the identified processor, generates presentation output comprising: (i) the performance metric, and (ii) information characterizing at least a portion of the proposed configuration of the storage system, and delivers the presentation output to the given client device over the network.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request from a process to access data is a system, determine if the data is in a virtualized protected area of memory in the system, and allow access to the data if the data is in the virtualized protected area of memory and the process is a trusted process. The electronic device can also be configured to determine if new data should be protected, store the new data in the virtualized protected area of memory in the system if the new data should be protected, and store the new data in an unprotected area of memory in the system if the new data should not be protected.

Abstract: A storage system according to an aspect of the present invention includes one or more storage devices for storing write data to which a write request from a host computer is directed, and a storage controller that provides one or more volumes to the host computer. Further, the storage system manages the time when a write request is last received from the host computer for each partition within the volume. Then, the storage controller performs a deduplication process upon detecting the partition not receiving a write request for a predetermined time or more from the time when the write request is last received.

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.

Abstract: A data processing system includes: a memory device suitable for performing an operation corresponding to a command and outputting a memory data; a data collecting device suitable for collecting big data by integrating the command and the memory data at a predetermined cycle or at every predetermined time, splitting the collected big data based on a predetermined unit, and transferring the split big data; and a data processing device suitable for storing the split big data received from the data collecting device in block-based files in a High-Availability Distributed Object-Oriented Platform (HADOOP) distributed file system (HDFS), classifying the block-based files based on a particular memory command, and processing the block-based files.