Patents Examined by Hiep T. Nguyen
  • Patent number: 11119668
    Abstract: Techniques are provided for managing incompressible data in a compression-enabled log-structured array storage system. A log-structured array is implemented in a block storage device having a physical storage space divided into logical data blocks (e.g., fixed-size allocation units), wherein the log-structured array includes a log segment which includes a set of contiguous logical data blocks of the physical storage space. When a write request is received to store data, if the received data is deemed compressible, the data is compressed and written in a log entry in the log segment of the log-structured array. If the data is deemed incompressible, the data is written without compression in a log entry in the log segment of the log-structured array such that the log entry which stores the data without compression is write-aligned to at least one logical data block of the set of contiguous logical data blocks of the log segment.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Itay Keller, Nir Milstein
  • Patent number: 11112992
    Abstract: An apparatus includes a generating unit and a copy unit. The generating unit generates and outputs first backup data including an information processing component and processing specifying information. The information processing component is included in the apparatus and includes identification information of a save area storing processing result data obtained through execution of a process defined by the information processing component. The processing specifying information uniquely identifies a process which is to be applied to the processing result data stored in the save area. The save area is included in the apparatus and is indicated by the identification information. When a person inputs an instruction to copy second backup data to the apparatus, if a first process matches a second process, the copy unit copies the information processing component in the second backup data to the apparatus. The second backup data is generated by the generating unit of a different apparatus.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: September 7, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventor: Toshiharu Hayashida
  • Patent number: 11112973
    Abstract: A computer system includes a host unit that issues a request of an I/O processing to a volume VOL, a local pool control unit that is in charge of management of a local pool based on a storage area of a drive of one node, and a global pool control unit that is in charge of management of a global pool based on a plurality of local pools, wherein the global pool control unit controls transmission of target data of the I/O processing performed by the host unit based on a commonality relationship among a first node that is formed with the host unit performing the I/O processing, a second node that is formed with the global pool control unit, and a third node that is formed with the local pool control unit managing the local pool.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 7, 2021
    Assignee: HITACHI, LTD.
    Inventors: Hiroto Ebara, Yoshinori Ohira, Hideo Saito, Masakuni Agetsuma, Takeru Chiba, Takahiro Yamamoto
  • Patent number: 11112980
    Abstract: A method of allocating a memory for driving a neural network including obtaining first capacity information of a space to store an input feature map of a first layer from among the layers of the neural network, and second capacity information of a space to store an output feature map of the first layer, and allocating a first storage space to store the input feature map in the memory based on an initial address value of the memory and the first capacity information and a second storage space to store the output feature map in the memory based on a last address value of the memory and the second capacity information.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joonho Song
  • Patent number: 11093172
    Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 17, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Masahiro Yoshihara
  • Patent number: 11093160
    Abstract: Techniques for determining snapshot compliance may include receiving policy information for a snapshot policy associated with a storage group of logical devices; receiving snapshot information regarding snapshots taken of the storage group during a time period denoting an amount of time corresponding to the retention time for the storage group; determining, based on the snapshot creation interval of the snapshot policy, a timeline of expected policy runtimes denoting different points in time at which the snapshot policy is scheduled to run to take a snapshot of the storage group; analyzing the snapshot information and the timeline to determine a number of valid snapshots of the storage group; and determining a compliance level for the time period based on the number of valid snapshots of the storage group and at least one compliance threshold.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Brian O'Halloran, Siobhan McLoughlin
  • Patent number: 11086525
    Abstract: Methods and apparatuses may be provided, where data is written to a first region of memory on a first memory appliance in response to a write operation, the first region of memory is external memory to the client device, and the first region of memory is accessible by the client device over a network via client-side memory access in which a first communication interface of the first memory appliance is configured to access the first region of memory on the first memory appliance; and where the data of the write operation is caused to be written to a second region of memory on a second memory appliance, and wherein the data of the write operation is recoverable from a subset of the memory regions, the subset excluding the first region of memory or the second region of memory.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 10, 2021
    Assignee: KOVE IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, Andrew S. Poling, Jesse I. Taylor, John Overton
  • Patent number: 11086796
    Abstract: A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Gerd Dirscherl, Bernd Meyer, Steffen Sonnekalb
  • Patent number: 11086555
    Abstract: A pod, the pod including the dataset, a set of managed objects and management operations, a set of access operations to modify or read the dataset, and a plurality of storage systems, where: management operations can modify or query managed objects equivalently through any of the storage systems, access operations to read or modify the dataset operate equivalently through any of the storage systems, each storage system stores a separate copy of the dataset as a proper subset of the datasets stored and advertised for use by the storage system, and operations to modify managed objects or the dataset performed and completed through any one storage system are reflected in subsequent management objects to query the pod or subsequent access operations to read the dataset.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 10, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Par Botes, John Colgrove, Alan Driscoll, David Grunwald, Steven Hodgson, Ronald Karr
  • Patent number: 11074005
    Abstract: Coordinated storage media verification is provided by checking usage of a plurality of storage media, maintaining a storage media check database indicating media verification to be performed for one or more of the plurality of storage media, where the maintaining includes determining and comparing a time since a last load of a selected storage medium to a verification frequency threshold and determining whether media verification of the selected storage medium is to be performed, coordinating media verification of at least one storage medium of the plurality of storage media based on the storage media check database, which coordinating includes selecting at least one storage medium to be verified in an ascertained window of time, and initiating media verification of the selected at least one storage medium.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sergio Varga, Douglas Luiz Mendes Baiense, Daniela Trevisan, Andre Luiz Coelho Silva
  • Patent number: 11070382
    Abstract: A method for authorizing I/O (input/output) commands in a storage cluster is provided. The method includes generating a token responsive to an authority initiating an I/O command, wherein the token is specific to assignment of the authority and a storage node of the storage cluster. The method includes verifying the I/O command using the token, wherein the token includes a signature confirming validity of the token and wherein the token is revocable.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 20, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Robert Lee, John Hayes
  • Patent number: 11068396
    Abstract: A method, computer program product, and computer system for staging writes into a log in chronological order, wherein each write may have a log record of a plurality of log records describing data of the write. The log record may be organized into a bucket of a plurality of buckets associated with a range of a plurality of ranges within a backing store, wherein each bucket of the plurality of buckets may include two keys respectively. The log record of the plurality of log records may be flushed from the bucket of the plurality of buckets to the backing store at a location and in an order determined based upon, at least in part, the two keys included with the bucket.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Socheavy D. Heng, William C. Davenport, Joris Johannes Wils
  • Patent number: 11061821
    Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
  • Patent number: 11055029
    Abstract: A storage system includes a storage controller that is configured to receive an input-output (IO) request and to obtain a flow control window size of the storage system. The flow control window size is dynamically adjustable by the storage controller based at least in part on an IO latency of the storage system. The storage controller is configured, in response to determining that an actual size of a portion of the IO request to be processed is greater than the flow control window size, to add an entry corresponding to the portion of the IO request to a flow control queue of the storage system with an indication that the portion of the IO request has an effective size equal to the flow control window size. The storage controller is further configured to process the entry in the flow control queue corresponding to the portion of the IO request using the actual size of the portion of the IO request.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Vladimir Shveidel
  • Patent number: 11055222
    Abstract: Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 6, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ilan Pardo, Noam Bloch
  • Patent number: 11055185
    Abstract: A storage manager for managing storage of files on a distributed logical volume includes a configuration manager configured to manage an archive of configurations of the distributed logical volume, and a snapshot manager configured to create a global snapshot of the distributed logical volume and, in response to a roll-back request, restore a previous global snapshot of the distributed logical volume based on a stored configuration of the distributed logical volume and stored subvolume snapshots of subvolumes of the distributed logical volume.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Eduard Shishkin
  • Patent number: 11054997
    Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
  • Patent number: 11042483
    Abstract: A computer system includes a cache and processor. The cache includes a plurality of data compartments configured to store data. The data compartments are arranged as a plurality of data rows and a plurality of data columns. Each data row is defined by an addressable index. The processor is in signal communication with the cache, and is configured to operate in a full cache purge mode and a selective cache purge mode. In response to invoking one or both of the full cache purge mode and the selective cache purge mode, the processor performs a pipe pass on a selected addressable index to determine a number of valid compartments and a number of invalid compartments, and performs an eviction operation on the valid compartments while skipping the eviction operation on the invalid compartments.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Deanna P. D. Berger, Vesselina Papazova
  • Patent number: 11016895
    Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
  • Patent number: 11016704
    Abstract: A semiconductor system may include a processor, a storage, a first memory apparatus and a second memory apparatus. The storage stores data by communicating with the processor. The first memory apparatus receives and stores data corresponding to a first workload and data corresponding to a second workload from the storage, and performs a first processing operation on the first workload, according to a request of the processor. The second memory apparatus receives the data corresponding to the second workload from the first memory apparatus, and performs a second processing operation on the second workload, according to a request of the processor.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Eui Seok Kim