Abstract: A data storage device is disclosed comprising a head actuated over a non-volatile storage medium. A plurality of access commands are received from a host and sored in a host queue and a pending queue. A first access command is selected from the host queue, wherein the first access command having a first execution time needed to execute the first access command. When a second access command in the pending queue can be executed within the first execution time, the second access command is executed, and after executing the second access command, the first access command in the host queue is executed. After selecting the first access command from the host queue, a third access command is transferred from the pending queue to the host queue based on a first-in-first-out (FIFO) order of the pending queue.

Abstract: An arithmetic processor, having: an arithmetic logical operation unit configured to execute an instruction; and a cache unit including a cache memory configured to store a part of data in a first main memory and a part of data in a second main memory which has a wider band than the first main memory when at least a predetermined capacity of data having consecutive addresses is accessed, and a cache control unit configured to read data in the cache memory responding to a memory request issued by the arithmetic logical operation unit and respond to the memory request source, wherein a ratio of capacity of the data in the second main memory with respect to the data in the first main memory stored in the cache memory is limited to a predetermined ratio or less.

Abstract: One embodiment facilitates data storage. During operation, the system selects a first page of a non-volatile storage to be recycled in a garbage collection process. The system determines that the first page is a first partial page which includes valid data and invalid data. The system combines the valid data from the first partial page with valid data from a second partial page to form a first full page, wherein a full page is aligned with a physical page in the non-volatile storage. The system writes the first full page to a first newly assigned physical page of the non-volatile storage.

Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.

Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

Abstract: One embodiment facilitates data placement in a storage device. During operation, the system receives, from a host, a request to read data. The system determines that the data is not available in a read cache. The system issues the read request to a solid state drive and a first hard disk drive. In response to unsuccessfully reading the requested data from the solid state drive and successfully reading the requested data from the first hard disk drive, the system sends the requested data to the host. In response to unsuccessfully reading the requested data from both the solid state drive and the first hard disk drive: the system issues the read request to a second hard disk drive; and the system sends the requested data to the host.

Abstract: A technique for managing data received into a cache operates in cycles. To process a current batch of compressed blocks during a current cache processing cycle, a storage system obtains a new mapping structure and a new segment of contiguous storage space. If the system can place some of the current batch of compressed blocks into previously-allocated space, the system does so and partially populates the new mapping structure with entries for mapping the other compressed blocks that were not placed. The system then asserts a hold on the new mapping structure, so that the mapping structure is retained in cache at the end of the current cache processing cycle, and more completely populates the new mapping structure with entries for other compressed blocks during a later cache processing cycle before releasing the hold.

Abstract: Techniques for processing I/O operations include: receiving a write I/O operation that writes first data to a target location, wherein the target location is represented as a logical device and offset within a logical address space of the logical device; storing a log record for the write I/O operation in a log file; and performing first processing of the log record. The log record includes log data, comprising the first data, and a log descriptor. The log descriptor includes a target logical address for the target location in a file system logical address space. The log descriptor includes a first value denoting the binary logarithm of an extent size of the first logical device. The first processing includes flushing the log record from the log file to store the first data of the log record on an extent of physical storage provisioned for the logical device.

Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.

Abstract: According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system.

Abstract: An IP-PBX system with the capability of automatic data backup and a method using the same is disclosed. The system includes one or more first devices, one or more second devices, and an IP-PBX having at least a first data storing area. The IP-PBX is installed with a verification program. The verification program verifies the backup permission of the first device or the second device when the first device or the second device reads the first data storing area. The first device is installed with a first control program and at least a backup verification code. The first control program drives a backup instruction set to automatically search the first data storing area and downloads the content of the first data storing area to the first device according to the backup verification code when the first device is electrically connected to the IP-PBX.

Abstract: Disclosed is a storage method of DNA digital data, including: encoding a plurality of bit data to a plurality of base sequences including at least one degenerate base; and synthesizing at least two types of bases constituting the at least one degenerate base on a substrate based on a mixing ratio.

Abstract: A method, information processing system, and computer readable storage medium, periodically monitor, with a processing system, information related to an application's memory usage including a maximum heap memory size and a garbage collection activity level. Based on determining that the garbage collection activity level is below a first threshold, releasing memory from the application by reducing the maximum heap memory size.

Abstract: Systems and methods for assisted indirect memory addressing are provided. Some computing systems move data between levels of a hierarchical memory system. To accommodate data movement for computing systems that do not natively support indirect addressing between levels of the memory hierarchy, a direct memory access (DMA) engine is used to fetch data. The DMA engine executes a first set of memory instructions that modify a second set of memory instructions to fetch data stored at one level of the memory hierarchy from dynamically computed indirect addresses stored in memory locations at another level of the memory hierarchy.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: A data processing system includes a host device and a memory system including a plurality of units. The host device includes a workload generation component and an analysis component. The workload generation component concurrently transmits, to the memory system, a plurality of commands for the plurality of memory units. The analysis component receives, from the memory system, command completion messages corresponding to the plurality of commands; measures latencies of the plurality of commands based on the receiving of the command completion messages; and analyze a parallelism scheme of the plurality of memory units based the measured latencies.

Abstract: Aspects of the disclosure provide a network device. The network device includes a search engine, a ternary content addressable memory (TCAM) cache engine, a search key generation unit and an output controller. The search engine stores a lookup table of entries for rules of packet processing, and searches the lookup table in response to packets received from a network interface of the network device. The TCAM cache engine caches a subset of the entries in the lookup table based on hit statistics of the entries. The search key generation unit generates a search key based on a received packet and provides the search key to the search engine and to the TCAM cache engine. The output controller outputs a search result from the TCAM cache engine when the TCAM cache engine has a matching entry to the search key.

Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

Abstract: Systems and methods for predicting the next host source of a command directed to a storage device, and configuring the storage device with the host memory configuration parameters of that predicted host, are disclosed. A predictive model may be used to identify which of a plurality of different actual or virtual hosts will be sending a next command based on a pattern of prior host origins of commands. The storage device may include a plurality of different memory configuration parameters associated with each different host source and may update the current memory configuration based on the predicted next host origin prior to actual receipt of a next command.