Abstract: Various embodiments described herein provide for extending a size of a memory unit of a memory device, such as a codeword of a page of the memory device, where the memory device can be included by a memory system. In particular, some embodiments implement extending (e.g., increasing) the size of a memory unit (e.g., codeword) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory unit while using a memory unit storage slot (e.g., codeword storage slot in a page) that is smaller in size than the extended memory unit.

Abstract: A system includes logic stored in the memory and executable by the processor to cause the processor to obtain the set of primary data objects and the set of residual data objects, each residual data object of the set of residual data objects being associated with, and representative of rounding that led to, a respective primary data object of the set of primary data objects, to evaluate, for each residual data object of the set of residual data objects, whether removal of the residual data object breaches a data integrity rule, to cause the processor to, for each residual data object of the set of residual data objects for which the removal breaches the data integrity rule, implement an optimization to attempt to identify at least one adjustment to the set of primary data objects, the set of residual data objects, or both the set of primary data objects and the set of residual data objects, that allows the removal to proceed without breaching the data integrity rule, to remove, from the set of residual data o

Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.

Abstract: Various embodiments provide an electronic device and method for determining the lifespan and failure of a nonvolatile memory storage device. The electronic device and the method according to various embodiments may be configured to determine whether the storage device has failed in response to a connection with the storage device, output a guidance message for replacing the storage device when the storage device fails, confirm whether the storage device has a function of autonomously identifying its state when the storage device is normal, check the lifespan of the storage device based on state information received from the storage device when the storage device has the function, estimate the lifespan of the storage device when the storage device does not have the function, and output the guidance message for replacing the storage device based on the lifespan.

Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

Abstract: A method for execution by a computing device of a storage network includes determining an encoded data slice reduction scheme for a set of encoded data slices stored in a set of storage units of the storage network, where a data segment of data is encoded into the set of encoded data slices in accordance with encoding parameters, and where the encoding parameters include a pillar width number and a decode threshold number. The method further includes maintaining storage of the set of encoded data slices in accordance with the encoded data slice reduction scheme, where the maintaining storage includes keeping a number of encoded data slices of the set of encoded data slices equal to or greater than the decode threshold number and less than the pillar width number.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: Apparatuses and methods can be related to performing prediction based garbage collection. Performing prediction based garbage collection can include performing a first instance of garbage collection, of the memory device, using a first circuitry of the controller and generating a prediction using a second circuitry of the controller. A confidence interval can also be generated for the prediction using the second circuitry of the controller. Responsive to determining that the confidence interval is greater than a threshold, a second instance of garbage collection, of the memory device, can be triggered using the first circuitry of the controller where the first instance of garbage collection is triggered before the second instance of garbage collection.

Abstract: Systems and methods for modifying a usage limit of a data storage device include a host interface; integrated circuit memory cells; and a processing device coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address, and configured to execute firmware to perform: operations requested by commands received via the host interface; and updates to a usage limit of the data storage device.

Abstract: A method, apparatus, and system determines an optimal storage configuration of storing backup data. The method may include receiving a request from a client device for determining an optimal storage configuration for storing backup data of a client. The method may include determining a cloud utilization pattern of the backup data based on prior access activities and determining a first suitability score for the first storage class based on the cloud utilization pattern. The method may include, for each of the storage classes of the first storage provider, determining a suitability score for the corresponding storage class if the backup data were stored in the corresponding storage class. The method may include transmitting to the client device a recommendation of a second storage class of the first storage provider having a suitability score higher than the first suitability score based on the suitability score to reduce cloud resources usage.

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

Abstract: In a particular embodiment, a dataset that is synchronously replicated across a plurality of storage systems is stored on a particular storage system. The storage system identifies input/output (I/O) requests directed to the dataset. The one or more I/O requests are initiated by an application hosted on a platform of the first storage system. The storage system services the one or more I/O requests directed to the dataset.

Abstract: A method of allocating a memory for driving a neural network including obtaining first capacity information of a space to store an input feature map of a first layer from among the layers of the neural network, and second capacity information of a space to store an output feature map of the first layer, and allocating a first storage space to store the input feature map in the memory based on an initial address value of the memory and the first capacity information and a second storage space to store the output feature map in the memory based on a last address value of the memory and the second capacity information.

Abstract: Embodiments of the present disclosure relate to autonomous data protection. An input/output (I/O) stream can be received for a storage device. One or more anomalies corresponding to the I/O stream can be identified. At least one of the one or more anomalies can be offloaded anomalies to a remote storage based on a capacity of memory allocated to store at least one snapshot of the storage device that include at least one of the one or more anomalies.

Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.

Abstract: Transitioning between replication sources for data replication operations, including: delaying a transition from using a first data repository as a source for data replication to using a second data repository as the source for data replication after detecting that one or more storage operations directed to the first data repository have not been replicated to the second data repository; and promoting the second data repository as the source for data replication such that storage operations received after completing the transition are directed to the second data repository.

Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

Abstract: A data processing apparatus and a vehicle having the same are provided. A data processing apparatus of a vehicle includes: a first memory having a plurality of storage areas to which each address of a plurality of addresses is allocated; and a processor configured to confirm information of data received from a first device, confirm an address corresponding to the received data based on the confirmed information of data, and store the received data in a storage area of the plurality of storage areas corresponding to the confirmed address.

Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.