Patents Examined by Hiep T. Nguyen
  • Patent number: 10482049
    Abstract: Configuring NVMe devices for redundancy and scaling includes: identifying, by a first SSD (‘Solid State Drive’) driver executing on a first CPU (‘Central Processing Unit’), address space of a first SSD coupled to the first CPU by a first PCI (‘Peripheral Component Interconnect’) switch, the first PCI switch including one or more non-transparent bridges (‘NTBs’); partitioning, by the first SSD driver, the address space of the first SSD amongst the NTBs of the first PCI switch and the first CPU, where each NTB is configured to translate CPU memory addresses received from a CPU into a drive address in the address space partitioned to the NTB; and partitioning, by the first SSD driver, a plurality of namespaces of the first SSD amongst the first CPU and the NTBs.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Patrick L. Caporale, Randolph S. Kolvick, Pravin Patel, Gregory B. Pruett, Theodore B. Vojnovich
  • Patent number: 10482019
    Abstract: Proposed are a storage apparatus and a control method thereof capable of improving the response performance to a read access of various access patterns. When data to be read is not retained in a data buffer memory, upon staging the data to be read, a processor performs sequential learning of respectively observing an access pattern in units of blocks of a predetermined size and an access pattern in units of slots configured from a plurality of the blocks regarding an access pattern of the read access from the host apparatus, and expands a data range to be staged as needed based on a learning result of the sequential learning.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 19, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Taku Adachi, Hisaharu Takeuchi
  • Patent number: 10474394
    Abstract: Example methods are provided to perform persistent reservation emulation in a shared virtual storage environment that includes a first host supporting a first node and a second host supporting a second node. One example method may comprise detecting a command issued by a first node to command issued by a first node to update information relating to a reservation or registration associated with a virtual disk, and updating persistent reservation information associated with the virtual disk to indicate that the command has been issued by the first node. The method may also comprise determining that the second node either has acknowledged the updated persistent reservation information, or has not acknowledged the updated persistent reservation information within a time interval. The method may further comprise updating the persistent reservation information based on the command.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 12, 2019
    Assignee: VMWARE, INC.
    Inventors: Rahul Dev, Gautham Swamy, Prasanna Aithal
  • Patent number: 10459824
    Abstract: Performing a cache-based trace recording using cache coherence protocol (CCP) data. Embodiments detect that an operation that causes an interaction between a cache line and a backing store has occurred, that logging is enabled for a processing unit that caused the operation, that the cache line is a participant in logging, and that the CCP indicates that there is data to be logged to a trace. Embodiments then cause that data to be logged to the trace, which data is usable to replay the operation.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 10452321
    Abstract: A storage system has a cluster structure in which a node is connected with a different node, the node having a volatile memory for storing first update data from a host and a first non-volatile memory for storing second copy data of second update data from the host to the different node, and having a copy management processing unit for storing first copy data of the first update data into a second non-volatile memory of the different node, and a storage service processing unit for transmitting, to the host, a response with respect to an update request of the first update data in response to the storage of the first copy data of the first update data by the copy management processing unit into the second non-volatile memory of the different node.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Hayasaka, Kazumasa Matsubara, Masanori Takada, Yoshihiro Yoshii
  • Patent number: 10445247
    Abstract: Methods, systems, and computer program products are included for switching from a first guest virtual address (GVA)-to-host physical address (HPA) translation mode to a second GVA-to-HPA translation mode. A method includes comparing, by a hypervisor, a number of translation lookaside buffer (TLB) misses to a miss threshold, the hypervisor being in a first GVA-to-HPA translation mode. The method includes switching from the first GVA-to-HPA translation mode to a second GVA-to-HPA translation mode if the number of TLB misses satisfies the miss threshold.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 15, 2019
    Assignee: Red Hat, Inc.
    Inventor: Bandan Souryakanta Das
  • Patent number: 10437508
    Abstract: A storage system, a computer program product and method for replicating a storage entity to a group of storage systems. The method may include splitting the storage entity, by a given storage system, to provide storage entity portions; generating, by the given storage system, storage entity portions information for distributing the storage entity portions between all storage systems of the group so that each storage system of the group eventually receives the storage entity portions; transmitting the storage entity portions, from the given storage system, to storage systems of the group; wherein the transmitting comprises transmitting different storage entity portions from the given storage system to different storage systems of the group; sending, by the given storage system, the storage entity portions information to at least some storage systems of the group; and attempting to verify, by the given storage system, that all the storage systems of the group received all the storage entity portions.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: October 8, 2019
    Assignee: .INFINIDAT LTD
    Inventor: Yoav Medan
  • Patent number: 10437495
    Abstract: A storage system in one embodiment comprises a host processor that includes a first non-volatile memory. The storage system further comprises a storage device that is coupled to the host processor. A designated portion of the first non-volatile memory is bound to the storage device responsive to storage of binding information in at least one partition table associated with the first non-volatile memory. The storage device may include a storage controller that includes a configuration register space. The binding information may be copied from the one or more partition tables to the configuration register space in conjunction with a boot operation of the host processor. The host processor illustratively comprises a storage device driver having access to the binding information copied to the configuration register space of the storage device. The storage device driver may be configured to utilize the designated portion of the first non-volatile memory that is bound to the storage device as a write back cache.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 8, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Adrian Michaud
  • Patent number: 10430098
    Abstract: Systems and methods of the present disclosure are directed to defining a data store format for storing state information related to border-gateway protocol (BGP) routing information base (RIB) entries, BGP Neighbor Tables, intermediate system-intermediate system (IS-IS) adjacencies, Link-State Databases, Interface information, Chassis information, etc in a binary format. A brick data store (BDS) system can define tables, table properties, objects and attributes for an application in the system using configuration files expressed in Java Script Object Notation (JSON). The data format can be uniform across inter-process communication, file and in-memory representation.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 1, 2019
    Assignee: RTBRICK, INC.
    Inventors: Hannes Gredler, Santosh Pallagatti Kotrabasappa, Deepak J, Pravin S. Bhandarkar
  • Patent number: 10416916
    Abstract: A Memory Merging Function “MMF” for merging memory pages. A hardware system comprises a set of memory blades and a set of computing pools. At least one instance of an operating system executes on the hardware system. The MMF is independent of the operating system. The MMF finds a first and a second memory page. The first and second memory pages include identical information. The first and second memory pages are associated with at least one computing unit of the computing units. The MMF obtains a respective memory blade parameter relating to memory blade of the first and second memory pages and a respective latency parameter relating to latency for accessing the first and second memory pages. The MMF releases at least one of the first and second memory pages based on the respective memory blade and latency parameters.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Amir Roozbeh, Joao Monteiro Soares, Daniel Turull
  • Patent number: 10416888
    Abstract: A parallel processing device includes a management unit, a plurality of nodes, and a controller that controls each of the plurality of nodes in accordance with a first command transmitted from the management unit. The controller includes a command storage that stores a second command generated a previous time, a command type identification unit that identifies a command type of the first command transmitted from the management unit, and a command generator that generates a third command by using the second command according to the command type.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Akihiro Waku
  • Patent number: 10402117
    Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 3, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nian Niles Yang, Idan Alrod
  • Patent number: 10402333
    Abstract: A computer system includes a main memory, a lower class memory, and a secondary storage medium and executes an operating system, an in-memory computing program, and a prefetch optimizer program. The in-memory computing program writes processing target data including a plurality of data objects stored in the secondary storage medium into a plurality of continuous areas on a virtual memory space and executes a process while accessing the continuous area. When detecting that the operating system executes a class-in process triggered upon a page fault for a predetermined virtual page, the prefetch optimizer program acquires information of the continuous area from the in-memory computing program and directs the operating system to execute a class-in process for virtual pages included in the predetermined continuous area including the predetermined virtual page.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: September 3, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Katsuto Sato, Nobukazu Kondo, Naruki Kurata
  • Patent number: 10394480
    Abstract: It is possible to prevent unoccupied blocks from being depleted by a write of logical-physical management information. A processor is capable of performing an unoccupied user block generation process by moving user data stored in allocated user blocks in order to generate unoccupied user blocks serving as unoccupied blocks among allocated user blocks, and performing an unoccupied meta block generation process by moving meta data stored in allocated meta blocks in order to generate unoccupied meta blocks serving as unoccupied blocks among the allocated meta blocks. The processor calculates the number of unoccupied meta blocks to be consumed, that is, the number of unoccupied meta blocks to be consumed by the unoccupied user block generation process. The processor performs the unoccupied meta block generation process based on the number of unoccupied meta blocks to be consumed.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 27, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Tsuruya, Ryo Hanafusa, Osamu Kawaguchi
  • Patent number: 10380056
    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Ian Shaeffer, Yi Lu
  • Patent number: 10372604
    Abstract: A method, information processing system, and computer readable storage medium, periodically monitor, with a processing system, information related to an application's memory usage including a maximum heap memory size, an in use heap memory size, and a garbage collection activity level. Based on determining that the garbage collection activity level is below a first threshold, estimating an amount of memory that can be released from the application by reducing the maximum heap memory size. Based on determining that the estimated amount of memory that can be released from the application is above a second threshold, attempting to release memory from the application.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Norman Bobroff, Arun Iyengar, Peter Westerink
  • Patent number: 10365832
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Patent number: 10354224
    Abstract: A clinical laboratory system for managing clinical laboratory work is described that includes: an examination information input means for inputting examination information relating to clinical laboratory work; an examination information memory means for storing input examination information; an extraction means for extracting examination information meeting a predetermined extraction condition related to progress of an examination from among stored examination information; a screen preparation means for creating a progress management screen for displaying extracted examination information; and an output means for outputting the progress management screen. Methods and computer programs for managing clinical laboratory work, management devices, and terminal devices are also described.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: July 16, 2019
    Assignee: SYSMEX CORPORATION
    Inventor: Ryuichi Tohma
  • Patent number: 10346046
    Abstract: An exemplary embodiment provides a non-transitory computer-readable storage medium with an executable information processing program stored thereon. The executable information processing program causes a computer of an information processing apparatus having a storage that stores a plurality of contents to perform designating an amount of data, selecting at least one content from among the plurality of contents based on the designated amount of data, and erasing the selected content from the storage in response to an operation by a user.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 9, 2019
    Assignee: NINTENDO CO., LTD.
    Inventors: Kouichi Kawamoto, Eiji Tokunaga, Masaaki Sugino
  • Patent number: 10346311
    Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr