Patents Examined by Hiep T. Nguyen
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Patent number: 11580049Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.Type: GrantFiled: December 27, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: James Brian Johnson, Brent Keeth
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Patent number: 11580039Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.Type: GrantFiled: November 16, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventor: Robert Walker
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Patent number: 11567693Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.Type: GrantFiled: June 15, 2021Date of Patent: January 31, 2023Assignee: SK hynix Inc.Inventors: Meysam Asadi, Aman Bhatia, Fan Zhang
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Patent number: 11550718Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for operating a cache drive in a data storage system. The methods include receiving, from an IO interface in the cache drive of the compute server, a write request to write data; caching the data corresponding to the write request in a cache storage of the cache drive of the compute server; performing one or more compute processes on the data; and in response to performing the one or more compute processes on the data, providing the processed data to a storage cluster for storing via the IO interface that is communicatively coupled to the storage cluster.Type: GrantFiled: November 10, 2020Date of Patent: January 10, 2023Assignee: Alibaba Group Holding LimitedInventor: Shu Li
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Patent number: 11544011Abstract: Methods and systems for a networked storage system are provided. One method includes: receiving, by a first storage node, a request to modify data stored using a logical storage object presented by the first storage node, the first storage node communicating with a second storage node configured as a failover partner of the first storage node; transmitting, by the first storage node, an invalidation request to the second storage node to invalidate an entry in a storage location cache of the second storage node, the entry indicating a storage location where data is stored by the first storage node, before modification; and responding, by the first storage node, to the request after modifying the data and upon receiving a response from the second storage node indicating successful invalidation of the entry.Type: GrantFiled: July 28, 2021Date of Patent: January 3, 2023Assignee: NETAPP, INC.Inventors: Sumith Makam, Rahul Thapliyal, Kartik R, Roopesh Chuggani, Abhisar Lnu, Maria Josephine Priyanka S
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Patent number: 11537326Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.Type: GrantFiled: February 22, 2021Date of Patent: December 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Uri Peltz, Karin Inbar
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Patent number: 11531487Abstract: Creating a replica of a storage system, including: receiving, by a first storage system from a computing device, data to be stored on the first storage system; reducing, by the first storage system, the data using one or more data reduction techniques; sending, from the first storage system to the second storage system, the reduced data, wherein the reduced data is encrypted; and sending, from the second storage system to a third storage system, the reduced data, wherein the reduced data is encrypted.Type: GrantFiled: July 24, 2020Date of Patent: December 20, 2022Assignee: PURE STORAGE, INC.Inventors: Ronald Karr, Constantine Sapuntzakis, John Colgrove
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Patent number: 11526277Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.Type: GrantFiled: January 25, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
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Patent number: 11520491Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.Type: GrantFiled: April 12, 2021Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Zhengang Chen
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Patent number: 11513693Abstract: One example method includes a splitter for data protection operations including replication operations. The splitter is located on or integrated into a smart network interface card and operates in two modes. The splitter is controlled by a replication controller. In one mode, the control path and the data path both go to the replication controller. In another mode, the data path is directly from the splitter to one or more targets without passing through the replication controller.Type: GrantFiled: October 13, 2020Date of Patent: November 29, 2022Assignee: EMC IP HOLDING COMPANY LLCInventor: Yossef Saad
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Patent number: 11507323Abstract: Embodiments of the present disclosure relate to a memory device and an operating method thereof. According to the embodiments of the present disclosure, when a read failure for a first read command among a plurality of read commands inputted from a memory controller occurs, the memory device may execute in an overlapping manner, a read retry operation for the first read command and a read operation for a second read command among the plurality of read commands.Type: GrantFiled: July 13, 2021Date of Patent: November 22, 2022Assignee: SK hynix Inc.Inventors: Chan Young Oh, Na Ra Shin
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Patent number: 11500752Abstract: A storage device is disclosed. A first storage media may store data. The first storage media may be of a first storage type and may be organized into at least two blocks. A second storage media may also store data. The second storage media may be of a second storage type different from the first type, and may also be organized into at least two blocks. A controller may manage reading data from and writing data to the first storage media and the second storage media. Metadata storage may store device-based log data for errors in the storage device. The drive-based log data may include a first log data for the first storage media and a second log data for the second storage media. An identification circuit may identify a suspect block in the at least two blocks in the first storage media and the second storage media, responsive to the device-based log data.Type: GrantFiled: November 9, 2020Date of Patent: November 15, 2022Inventors: Nima Elyasi, Changho Choi
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Patent number: 11494112Abstract: Disclosed is a method for maintaining operation log information stored in a non-volatile memory of a storage device. The method includes the steps of: configuring a buffer area of a volatile memory; caching the operation log information into the buffer area; writing the operation log information stored in the buffer area into a predetermined storage area of the non-volatile memory; repeatedly updating the operation log information to the predetermined storage area; and initializing the storage device, which includes the following steps of enabling a watchdog timer in a controller; fetching the latest operation log information by reading the predetermined storage area when the watchdog timer counts a predetermined time and the storage device does not complete the initialization; configuring the storage device to perform a force low-level formatting after the latest operation log information is fetched; and disabling the watchdog timer when the storage device completes the initialization.Type: GrantFiled: July 27, 2021Date of Patent: November 8, 2022Assignee: RAYMX MICROELECTRONICS CORP.Inventors: Yinghui Fu, Xin Liu
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Patent number: 11487461Abstract: Techniques for preventing recovery of specific data elements based on a recovery prevention configuration defined by a user are disclosed. In some embodiments, a computer system performs operations comprising: receiving a recovery prevention configuration from a first computing device of a first user, the recovery prevention configuration comprising at least one recovery prevention parameter specified by the first user via one or more user interface elements displayed on the first computing device, the at least one recovery prevention parameter being configured to identify one or more backup data elements stored in a secondary storage system; storing the recovery prevention configuration in a database in association with the secondary storage system; and filtering out the one or more backup data elements stored in the secondary storage system from a data recovery process based on the at least one recovery prevention parameter of the stored recovery prevention configuration.Type: GrantFiled: January 29, 2021Date of Patent: November 1, 2022Assignee: Rubrik, Inc.Inventors: Fabiano Botelho, Soham Mazumdar, Arvind Nithrakashyap
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Patent number: 11487439Abstract: Storage devices include a memory array which stores host data received from a host computing device. During normal operations, the storage device may encounter a fatal error which can halt functionality. To restore functionality without system disconnection or third-party interventions, the storage device can store recovery data within a host memory buffer prior to encountering a fatal error. The recovery data can be replay protected memory data and/or firmware recovery data that can be written to the host memory buffer upon power on or during a firmware update. When a fatal error occurs, the recovery data can be accessed to try and rebuild file and mapping systems to restore full operation of the storage device. When full operational restoration is not possible, host data can at least be copied from the storage device prior to utilizing firmware recovery data to restore the storage device to an erased but functional state.Type: GrantFiled: May 27, 2021Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Kiran Kumar Eemani, Sridhar Prudviraj Gunda, Shivam Chawla, Vikram Kumar
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Patent number: 11481123Abstract: Methods, systems, and devices for techniques for failure management in memory systems are described. A memory system may include one or more non-volatile memory devices. A set of physical blocks of memory cells of the one or more non-volatile memory devices may be grouped into virtual blocks, where each physical block of a virtual may block may be within a different plane of the one or more non-volatile memory devices. The memory system may detect a failure within a physical block of a virtual block and may transfer data from the physical block to one or more other physical blocks within the same virtual block in response to detecting the failure.Type: GrantFiled: April 27, 2021Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 11461263Abstract: A system and method for managing memory resources. In some embodiments, the system includes a first memory server, a second memory server, and a server-linking switch connected to the first memory server and to the second memory server. The first server may include a cache-coherent switch and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, and the cache-coherent switch is connected to the server-linking switch.Type: GrantFiled: September 18, 2020Date of Patent: October 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Krishna Teja Malladi, Byung Hee Choi, Andrew Chang, Ehsan M. Najafabadi
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Patent number: 11461050Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enforcing a decay policy for a data object. One of the methods includes receiving a request to store a data object in a storage device; obtaining a user policy identifying a lifetime of the data object; determining, using the lifetime of the data object, a voltage policy for a plurality of memory cells of the storage device, wherein: each of the plurality of memory cells will store one or more bits of the data object; the voltage policy identifies a voltage to provide each memory cell; and an expected time at which raw bit errors of the data object will cause the data object to decay is equal to a time point identified by the lifetime of the data object; and storing the data object in the storage device according to the determined voltage policy.Type: GrantFiled: January 20, 2021Date of Patent: October 4, 2022Assignee: VMware, Inc.Inventors: Amy Tai, Michael Wei
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Patent number: 11461025Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.Type: GrantFiled: November 5, 2020Date of Patent: October 4, 2022Assignee: Macronix International Co., Ltd.Inventors: Shuo-Nan Hung, E-Yuan Chang
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Patent number: 11455101Abstract: Information pertinent to a connectivity issue reported by a switch may be determined, compiled and reported; and action may be taken autonomously to address the connectivity issue based on the information. The additional information may be determined by the storage system, including querying a switch in response to the switch notifying the storage system of the I/O error, and the storage system accessing one or more data structures to determine additional information. The storage system may cause I/O communications on the I/O path to be at least temporarily diverted. For example, in response to receiving an I/O request on the I/O path corresponding to the connectivity issue, the storage system may send a communication to the host system that causes the host system not to send additional I/O requests on the I/O path, at least temporarily, as described in more detail elsewhere herein.Type: GrantFiled: September 30, 2020Date of Patent: September 27, 2022Assignee: EMC IP Holding Company LLCInventors: Alan Rajapa, Scott Rowlands, Erik P. Smith, Igor Fradkin, Arieh Don