Patents Examined by Hiep T. Nguyen
  • Patent number: 11226920
    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 11221801
    Abstract: A data writing method and a storage controller are provided. The data writing method includes: selecting a plurality of first dies and a plurality of second dies from a plurality of dies of the flash memory module, receiving a writing command and determining an amount of write data corresponding to the writing command, and when the amount of write data is greater than a threshold, writing in a pSLC mode the write data into the second dies.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 11, 2022
    Assignee: Acer Incorporated
    Inventors: Guan-Yu Hou, Tz-Yu Fu
  • Patent number: 11216386
    Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Vivek Kozhikkottu, Suresh Chittor, Esha Choukse, Shankar Ganesh Ramasubramanian
  • Patent number: 11216205
    Abstract: A checkpoint server for containers is disclosed. The checkpoint server generates checkpoint images of running containers or of warmed-up containers. These checkpoint images are restored such that the order in which memory pages are accessed can be recorded or logged. During a restore operation to a host, the memory pages are transmitted in accordance with the page order log. The container can then begin serving requests before all of the memory pages have been transmitted to the host.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: January 4, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Victor Fong, Kenneth Durazzo
  • Patent number: 11194504
    Abstract: Efficient pre-reading is performed in data transmission and reception between an Edge node and a Core node. An information processing device includes a storage device, outputs client request data based on a request of a client, and stores predetermined pre-read data in the storage device before the request of the client. The device includes: a relevance calculation module configured to calculate relevance between data based on an access history of the data; and a pre-reading and deletion module configured to determine data to be deleted from the storage device using the relevance when data having predetermined relevance with the client request data is to be stored to the storage device as the pre-read data and a storage capacity of the storage device is insufficient if at least one of the client request data and the pre-read data is to be stored to the storage device.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 7, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kazumasa Matsubara, Mitsuo Hayasaka
  • Patent number: 11194732
    Abstract: A memory controller for controlling a memory device including a plurality of pages is provided. The memory controller comprises: an input data controller configured to receive data to be stored in a page selected from among the plurality of pages; a sequence information generator configured to generate sequence information indicating a sequential order of a program operation of storing the data in the first page based on sequential orders of program operations performed before the program operation; and a write operation controller configured to control the memory device to store the data in a first area of the first page and to store history information in a second area of the first page, wherein the history information includes a physical address of the first page and the sequence information corresponding to the data.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun Sik Oh, Seok Jin Kwon
  • Patent number: 11194514
    Abstract: A memory system includes a memory array and a memory controller. The memory array includes a plurality of memory dies communicatively coupled via a plurality of memory channels, each memory channel communicatively coupled to a subset of the plurality of memory dies. The memory controller includes a command scheduler configured to determine an operator status of each memory die of the memory array, determine, based on the operator status of each of the memory dies, an order in which to output commands to the memory dies, update a mapping table based on the determined order in which to output the commands to the memory dies of the memory array, and output the commands to the memory dies of the memory array in the determined order in the mapping table.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 7, 2021
    Assignee: Kioxia Corporation
    Inventor: Randy Brown
  • Patent number: 11188248
    Abstract: A pass-through snapshot engine records lifecycle data and chronological status of files or objects, in one or more pass-through snapshots during a backup. If there is an abort, the pass-through snapshot engine freezes the pass-through snapshot(s) and terminates the backup. To restart after the abort, the pass-through snapshot engine sends one or more pass-through snapshots to the backup agent. The backup agent restarts the backup, and enforces states of lifecycle and chronology to files or objects, and discards files or objects that have already been backed up to the target device, in accordance with the one or more pass-through snapshots.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 30, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mahesh Reddy A V, Chetan Battal, Swaroop Shankar D H, Mahantesh Ambaljeri
  • Patent number: 11177006
    Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Steve Kientz
  • Patent number: 11163496
    Abstract: Techniques for updating persistent statistics on a multi-transactional and multi-node storage system. The techniques can be practiced in a distributed storage system including a plurality of storage nodes. Each storage node can include a persistent storage configured to accommodate a set of delta counter pages, as well as a global counter page for summarizing delta count values tracked by respective delta counters. The techniques can include, in each storage node, tracking, by each of a set of delta counters, changes to delta count values due to storage node operations performed on units of data storage, and summarizing, periodically or at least at intervals, the delta count values of the respective delta counters as global count values. The techniques can further include summarizing the global count values across the respective storage nodes in a count summarization report and sending the count summarization report to a client via a communications interface.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Vamsi K. Vankamamidi, Yubing Wang, Ajay Karri
  • Patent number: 11157199
    Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11144233
    Abstract: Described is a system for managing point-in-time backups (or “snapshots”) of data that are stored as part of a primary storage. As part of a data protection service, a set of snapshots may be stored on the primary storage system for efficient and immediate recovery, and a set of corresponding recovery snapshots may be stored on a secondary storage system for recovery purposes. Accordingly, the system may provide the ability to leverage the efficient storage mechanisms of the primary storage, while still maintaining the data storage efficiency (e.g. costs) of the secondary storage. Moreover, the system may manage the snapshots stored on the primary and secondary storages independently. For example, the system may fully leverage the available capacity of storage pools within the primary storage by automatically purging certain snapshots from the primary storage while still maintaining the corresponding recovery snapshots on the secondary storage.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Upanshu Singhal, Sanjeev Kumar Lohchab
  • Patent number: 11144209
    Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for managing an input/output (I/O). The method comprises, in response to receiving a first I/O request of a first type for a storage device, determining whether there exists at least one credit available to the first type of I/O requests. Each of the at least one credit indicates I/O processing capability reserved by the storage device for the first type of I/O requests. The method further comprises allocating a first credit to the first I/O request based on a result of the determining. The method further comprises performing, by using the first credit, an I/O operation requested by the first I/O request on the storage device. Moreover, the method further comprises, in response to completion of the I/O operation, recycling the first credit for use by a subsequent I/O request. Embodiments of the present disclosure can implement dynamic allocation of I/O processing capability for different types of I/Os.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: Lifeng Yang, Xinlei Xu, Liam Li, Ruiyong Jia, Yousheng Liu
  • Patent number: 11144213
    Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Intemational Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Jared M. Minch, Beth A. Peterson
  • Patent number: 11137943
    Abstract: Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John Traver, Ning Zhao, Tom V. Geukens, Yun Li
  • Patent number: 11138120
    Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong-Woo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung, Chan-Jong Woo
  • Patent number: 11127479
    Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining a margin between the CDF-based data at a particular codeword frequency and one of the thresholds.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, David Miller
  • Patent number: 11119663
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform a data integrity check of copies of a data set. Input on storage attributes of a plurality of storage units, each storage unit of the storage units storing a copy of a data set, is provided to a machine learning module to produce an output value. A determination is made as to whether the output value indicates to perform a data integrity check of the copies of the data set. A determination is made as to whether the copies of the data set on different storage units are inconsistent in response to determining to perform the data integrity check. At least one of the copies of the data set is corrected to synchronize all the copies of the data set.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta
  • Patent number: 11119944
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 14, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 11119662
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform a data integrity check of copies of a data set. Input on storage attributes of a plurality of storage units, each storage unit of the storage units storing a copy of a data set, is provided to a machine learning module to produce an output value. A determination is made as to whether the output value indicates to perform a data integrity check of the copies of the data set. A determination is made as to whether the copies of the data set on different storage units are inconsistent in response to determining to perform the data integrity check. At least one of the copies of the data set is corrected to synchronize all the copies of the data set.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta