Abstract: In a preferred embodiment, the gain expansion in low power mode of a single chain PA is minimized by dynamically adjusting the output impedance of the bias circuit of each gain stage for each mode of operation. Instead of switching in a series attenuator or switching in additional feedback in the first gain stage of a single-chain PA to limit the gain at the increased quiescent current level, this embodiment achieves linear performance by adjusting the quiescent current in each stage to the minimum level that meets the target gain and then increasing the output resistance of the bias circuit of each gain stage in low power mode (LPM) to provide the appropriate level of negative feedback at the base of each amplifying HBT to linearize the gain versus power response.

Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

Abstract: Amplifiers can be used for a variety of electronic-based applications. Therefore, amplifier performance is of importance. A low noise amplifier can be interfaced after an antenna or a band-select filter as a first active stage, in a receiver since its bandwidth characteristics can be closely related to a system data rate. A bandwidth enhancement technique can be leverage for low noise amplifiers by embedding a transformer between a gate and a drain terminal of a common gate transistor in a cascode topology. The embedded transformer can introduce an additional high-frequency conjugate zero pair, which can push the gain rolling-off start-up point to a higher frequency, peak the higher frequency gain, and broaden the low noise amplifier gain bandwidth.

Abstract: A semiconductor integrated circuit includes a transformer that includes a first winding and a second winding, a low-noise amplifier circuit that includes an input terminal in which at least one end of the second winding of the transformer is connected to the input terminal; and a switch that is provided between the one end and another end of the second winding of the transformer. The switch is opened and the transformer functions as an input impedance matching circuit for the low-noise amplifier circuit in a period in which a reception signal is supplied to the first winding of the transformer. On the other hand, the switch is closed and the transformer is caused to become an element including a predetermined capacitance in a period in which another circuit connected to the predetermined node operates.

Abstract: A power amplifier comprising a first, a second and a third sub-amplifier for amplification of an input signal into an output signal. The sub-amplifiers are connected to an output network for providing the output signal at an output port of the output network. The output network comprises a first, a second and a third transmission line connected to the first sub-amplifier, the second sub-amplifier, and the third sub-amplifier, respectively. The first and second sub-amplifiers are operable in a first mode. The second and third sub-amplifiers are operable in a second mode. The first and third sub-amplifiers are operable in a third mode. Each of the first, second and third modes comprises a respective out-phasing mode in a respective part of an amplitude range of the power amplifier.

Abstract: A semiconductor includes a semiconductor substrate having first and second opposite facing surfaces. An amplifier device is formed in the semiconductor substrate, the amplifier device is configured to amplify an RF signal at a fundamental frequency. A first dielectric layer is formed on the first surface of the substrate. A first metallization layer is formed on the first dielectric layer. The first metallization layer is spaced apart from the substrate by the first dielectric layer. The first metallization layer includes a first elongated finger interdigitated with a first reference potential pad. The first elongated finger is physically disconnected from the first reference potential pad. The first reference potential pad includes a first patterned shape that is devoid of metallization. The first patterned shape has a geometry that filters harmonic components of the fundamental frequency.

Abstract: A low noise amplifier circuit includes a first amplifier including a first transistor and a second transistor that are cascode-connected to each other; a second amplifier including a third transistor and a fourth transistor that are cascode-connected to each other; a source terminal matcher connected to a source of the first transistor and a source of the third transistor; and an input matcher providing input that is impedance-matched by a first inductor and a second inductor to a gate of the first transistor and providing input which is impedance-matched by the first inductor to a gate of the third transistor. The circuit is able to operate in a dual-band and provide impedance matching, while being simpler than alternative circuits.

Abstract: A device, system and method for a wideband low noise amplifier is provided. The device may include a main amplifier and an error amplifier. In each amplifier is a phase inverter configured to invert the incoming signal. Additionally, rather than being formed from discrete components, the conductors of this wideband low noise amplifier are formed from microwave monolithic integrated circuits to provide for greater efficiency, which enables the low noise amplifier to operate in wideband rather than narrowband. A method of using the same is also provided.

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Abstract: A circuit for amplifying a source signal generated by a signal source having a first impedance includes a transmission line transformer (TLT) having a first, a second, a third, and a fourth port wherein the TLT is coupled to receive the source signal at the first port and configured to output a corresponding impedance matched signal at the second port, the second port is coupled to the third port of the TLT, the circuit also including a TLT load having a first terminal coupled to the fourth port of the TLT and a second terminal coupled to a reference potential. The circuit additionally includes an amplifier device responsive to the impedance matched signal to generate an amplified signal.

Abstract: A reconfigurable load modulation amplifier having a carrier amplifier and a peak amplifier that are coupled in parallel is disclosed. The peak amplifier provides additional power amplification when the carrier amplifier is driven into saturation. A quadrature coupler coupled between the carrier amplifier and the peak amplifier is configured to combine power from both the carrier amplifier and the peak amplifier for output through an output load terminal. The reconfigurable load modulation amplifier further includes control circuitry coupled to an isolation port of the quadrature coupler and configured to provide adjustable impedance at the isolation port of the quadrature coupler. As such, impedance at the isolation port of the quadrature coupler is tunable such that at least a carrier or peak amplifier is presented with a quadrature coupler load impedance that ranges from around about half an output load termination impedance to around about twice the output load termination impedance.

Abstract: An amplifier that is configured to amplify an RF signal includes a power combiner circuit. The power combiner circuit includes a first branch connected between a first RF input port and a summing node and a second branch connected between a second RF input port and the summing node. Each of the first and second branches includes an impedance inverter. The Chireix combiner is configured to present a Chireix load modulated impedance response to the first and second RF input ports. The power combiner circuit further includes compensation elements being configured to at least partially compensate for a reactance of the Chireix combiner circuit in a Doherty amplifier mode in which a signal is applied to the first RF input port and the second RF input port is electrically open.

Abstract: A Doherty power amplifier includes a main power amplification circuit, an auxiliary power amplification circuit, a connection circuit, and an impedance conversion circuit. An output end of the main power amplification circuit and an output end of the auxiliary power amplification circuit are connected to two ends of the connection circuit separately by using bonding wires. The output end of the auxiliary power amplification circuit is further connected to one end of the impedance conversion circuit by using a bonding wire, and the other end of the impedance conversion circuit is connected to an output load.

Abstract: This disclosure provides isolation for a medical amplifier by providing a low impedance path for noise across an isolation barrier. The low impedance path can include a capacitive coupling between a patient ground, which is isolated from control circuitry, and a functional ground of an isolation system that is isolated from earth ground. The low impedance path can draw noise current from an input of an amplifier of patient circuitry.

Abstract: An apparatus includes multiple field effect transistors and multiple wires. An input wire may be configured to transfer an input signal along an axis. The field effect transistors may be configured to generate a pair of intermediate signals by amplifying the input signal. Multiple gates of the field effect transistors may be configured to receive the input signal. A topology of the gates may be rotated to be perpendicular to the axis. The field effect transistors may be located in two rows mirrored about the axis. Intermediate wires may be configured to transfer the intermediate signals parallel to the axis. A collection wire may be configured to transfer the intermediate signals toward each other and generate an output signal by combining the intermediate signals. An output wire may be configured to transfer the output signal parallel to the axis and away from the field effect transistors.

Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Abstract: The present invention aims to provide a digital variable capacitance circuit, a resonant circuit, an amplification circuit, and a transmitter having a high performance. A digital variable capacitance circuit 50 according to this embodiment is a digital variable capacitance circuit including a plurality of unit capacity cells 51-0 to 51-n connected in parallel between two output terminals OUTP and OUTN, in which the unit capacity cell 51 comprises: a first capacitor Cu1 having one end connected to one output terminal OUTP; a second capacitor Cu2 that is connected in series with the first capacitor Cu1 between the two output terminals; and an NMOS transistor M1 that is connected in parallel with the second capacitor Cu2 and is controlled in accordance with a digital control signal.

Abstract: A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

Abstract: An amplifier circuit with an overshoot suppress scheme is provided. The amplifier circuit includes an input amplifier, an output amplifier and a diode device. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

Abstract: Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.