Patents Examined by Hoa B. Trinh
  • Contact integration and selective silicide formation methods
    Patent number: 10964544
    Abstract: Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550° C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 30, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Matthias Bauer
  • Molding compound including a carbon nano-tube dispersion
    Patent number: 10953593
    Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound are disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Myung Jin Yim, Jason M. Brand
  • Semiconductor device package
    Patent number: 10950529
    Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Soonheung Bae, Hyunjoung Kim
  • Light-emitting device and method of preparing same, optical semiconductor element mounting package, and optical semiconductor device using the same
    Patent number: 10950767
    Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 16, 2021
    Assignee: SHENZHEN JUFEI OPTOELECTRONICS CO., LTD.
    Inventors: Naoyuki Urasaki, Kanako Yuasa
  • Buffer design for package integration
    Patent number: 10930633
    Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Semiconductor device
    Patent number: 10923561
    Abstract: A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: February 16, 2021
    Assignee: DENSO CORPORATION
    Inventor: Motoo Yamaguchi
  • Asymmetric threshold voltage FinFET device by partial channel doping variation
    Patent number: 10916659
    Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Choonghyun Lee, Pouya Hashemi, Takashi Ando, Jingyun Zhang
  • Self-aligned contact for vertical field effect transistor
    Patent number: 10896972
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • BEOL alternative metal interconnects: integration and process
    Patent number: 10886225
    Abstract: Back-end-of-the line (BEOL) interconnect structures are provided in which an alternative metal such as, for example, a noble metal, is present in a combined via/line opening that is formed in an interconnect dielectric material layer. A surface diffusion dominated reflow anneal is used to reduce the thickness of a noble metal layer outside the combined via/line opening thus reducing or eliminating the burden of polishing the noble metal layer. In some embodiments and after performing the anneal, a lesser noble metal layer can be formed atop the noble metal layer prior to polishing. The use of the lesser noble metal layer may further reduce the burden of polishing the noble metal layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theo Standaert
  • Improving size and efficiency of dies
    Patent number: 10886228
    Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Jonathan Rosenfeld
  • Electrically or temperature activated shape-memory materials for warpage control
    Patent number: 10861797
    Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Bret K. Street
  • Semiconductor device and method for manufacturing same
    Patent number: 10854534
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Electronic devices with bond pads formed on a molybdenum layer
    Patent number: 10840179
    Abstract: An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Ting-Ta Yen, Brian E. Goodlin
  • Packages with stacked dies and methods of forming the same
    Patent number: 10825798
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Tsung-Ding Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Semiconductor package system and related methods
    Patent number: 10825748
    Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • Substrate panel structure and manufacturing process
    Patent number: 10818636
    Abstract: A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 27, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Jen-Kuang Fang
  • Power semiconductor module with heat dissipation plate
    Patent number: 10818573
    Abstract: An object of the present invention is to provide a structure, particularly, a power semiconductor module, which suppresses a bypass flow of a cooling medium and improves cooling efficiency. A structure according to the present invention includes a heat dissipation plate thermally connected to a heating element, and a resin region having a resin material that fixes the heating element and the heat dissipation plate, wherein the heat dissipation plate includes a fin portion including a plurality of fins protruding from a heat dissipation surface of the heat dissipation plate and formed to be exposed from the sealing resin material, and a wall portion formed to protrude from the heat dissipation surface to a same side as the fin and which separates the fin portion and the resin region.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: October 27, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Nobutake Tsuyuno, Takeshi Tokuyama, Eiichi Ide
  • Multi-LED system
    Patent number: 10818641
    Abstract: A multi-LED system is disclosed. In an embodiment a multi-LED system includes a ceramic multilayer substrate in which at least two ESD protection structures are integrated, at least two light-emitting diodes arranged on the substrate and at least two capping layers covering one of the light-emitting diodes.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: October 27, 2020
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Stephan Steinhauser, Günter Pudmich, Edmund Payr, Sebastian Brunner
  • Interconnect structure and method of forming same
    Patent number: 10811374
    Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Method of manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same
    Patent number: 10811302
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung II Kang, In Seob Bae, Jea Won Kim