Abstract: Back-end-of-the line (BEOL) interconnect structures are provided in which an alternative metal such as, for example, a noble metal, is present in a combined via/line opening that is formed in an interconnect dielectric material layer. A surface diffusion dominated reflow anneal is used to reduce the thickness of a noble metal layer outside the combined via/line opening thus reducing or eliminating the burden of polishing the noble metal layer. In some embodiments and after performing the anneal, a lesser noble metal layer can be formed atop the noble metal layer prior to polishing. The use of the lesser noble metal layer may further reduce the burden of polishing the noble metal layer.
Type:
Grant
Filed:
March 5, 2018
Date of Patent:
January 5, 2021
Assignee:
International Business Machines Corporation
Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.
Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
Abstract: An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.
Type:
Grant
Filed:
February 19, 2018
Date of Patent:
November 17, 2020
Assignee:
TEXAS INSTRUMENTS INCORPORATED
Inventors:
Ricky Alan Jackson, Ting-Ta Yen, Brian E. Goodlin
Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.
Abstract: A multi-LED system is disclosed. In an embodiment a multi-LED system includes a ceramic multilayer substrate in which at least two ESD protection structures are integrated, at least two light-emitting diodes arranged on the substrate and at least two capping layers covering one of the light-emitting diodes.
Type:
Grant
Filed:
March 21, 2017
Date of Patent:
October 27, 2020
Assignee:
EPCOS AG
Inventors:
Thomas Feichtinger, Stephan Steinhauser, Günter Pudmich, Edmund Payr, Sebastian Brunner
Abstract: An object of the present invention is to provide a structure, particularly, a power semiconductor module, which suppresses a bypass flow of a cooling medium and improves cooling efficiency. A structure according to the present invention includes a heat dissipation plate thermally connected to a heating element, and a resin region having a resin material that fixes the heating element and the heat dissipation plate, wherein the heat dissipation plate includes a fin portion including a plurality of fins protruding from a heat dissipation surface of the heat dissipation plate and formed to be exposed from the sealing resin material, and a wall portion formed to protrude from the heat dissipation surface to a same side as the fin and which separates the fin portion and the resin region.
Type:
Grant
Filed:
August 26, 2015
Date of Patent:
October 27, 2020
Assignee:
Hitachi Automotive Systems, Ltd.
Inventors:
Nobutake Tsuyuno, Takeshi Tokuyama, Eiichi Ide
Abstract: A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.
Type:
Grant
Filed:
August 30, 2018
Date of Patent:
October 27, 2020
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
Type:
Grant
Filed:
January 16, 2019
Date of Patent:
October 20, 2020
Assignee:
Intel Corporation
Inventors:
Feras Eid, Robert L. Sankman, Sandeep B. Sane
Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
Type:
Grant
Filed:
May 31, 2017
Date of Patent:
October 13, 2020
Assignee:
Tessera, Inc.
Inventors:
Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
Type:
Grant
Filed:
June 7, 2018
Date of Patent:
October 6, 2020
Assignee:
Intel Corporation
Inventors:
Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
Abstract: Provided is a composition for forming a film for semiconductor devices, including: a compound (A) including a Si—O bond and a cationic functional group containing at least one of a primary nitrogen atom or a secondary nitrogen atom; a crosslinking agent (B) which includes three or more —C(?O)OX groups (X is a hydrogen atom or an alkyl group having from 1 to 6 carbon atoms) in the molecule, in which from one to six of three or more —C(?O)OX groups are —C(?O)OH groups, and which has a weight average molecular weight of from 200 to 600; and a polar solvent (D).
Type:
Grant
Filed:
November 16, 2016
Date of Patent:
August 25, 2020
Assignee:
MITSUI CHEMICALS, INC.
Inventors:
Yasuhisa Kayaba, Hirofumi Tanaka, Koji Inoue
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
Type:
Grant
Filed:
March 15, 2018
Date of Patent:
August 25, 2020
Assignees:
UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
Type:
Grant
Filed:
August 31, 2017
Date of Patent:
August 11, 2020
Assignee:
Infineon Technologies AG
Inventors:
Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert