Patents Examined by Hoa B. Trinh
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Patent number: 10446527Abstract: Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.Type: GrantFiled: September 11, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventor: Eiichi Nakano
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Patent number: 10446460Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.Type: GrantFiled: March 7, 2018Date of Patent: October 15, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
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Patent number: 10446774Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.Type: GrantFiled: January 13, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yi-Koan Hong, Kwang-Jin Moon, Nae-In Lee, Ho-Jin Lee
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Patent number: 10446535Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.Type: GrantFiled: April 25, 2016Date of Patent: October 15, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexandre Ayres, Bertrand Borot
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Patent number: 10438902Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.Type: GrantFiled: September 7, 2017Date of Patent: October 8, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Vincent J. McGahay, Nicholas A. Polomoff, Shaoning Yao, Anupam Arora
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Patent number: 10439017Abstract: A display apparatus includes a substrate having a first area, a second area, and a bending area disposed therebetween. The substrate is bent at the bending area about a bending axis. An inorganic insulating layer is disposed over the substrate and includes an opening or groove corresponding to the bending area. An organic material layer fills the opening or groove. A first conductive layer extends from the first area to the second area through the bending area. The first conductive layer is disposed over the organic material layer and includes a multipath portion having a plurality of through holes. A length of the multipath portion, in a direction from the first area to the second area, is greater than a width of the opening or groove, in the direction from the first area to the second area.Type: GrantFiled: December 5, 2017Date of Patent: October 8, 2019Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Dongsoo Kim, Wonkyu Kwak, Kwangmin Kim, Kiwook Kim, Joongsoo Moon, Hyunae Park, Jieun Lee, Changkyu Jin
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Patent number: 10431516Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.Type: GrantFiled: February 21, 2017Date of Patent: October 1, 2019Assignee: ROHM CO., LTD.Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
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Patent number: 10431547Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.Type: GrantFiled: January 13, 2018Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geol Nam, Young Lyong Kim
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Patent number: 10424571Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.Type: GrantFiled: September 6, 2017Date of Patent: September 24, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Choi, Eun-Seok Song, Seung-Yong Cha, Yun-Hee Lee
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Patent number: 10395980Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.Type: GrantFiled: February 21, 2018Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Motoi Ichihashi, Atsushi Ogino
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Patent number: 10373844Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.Type: GrantFiled: May 9, 2017Date of Patent: August 6, 2019Assignee: INTEL IP CORPORATIONInventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
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Patent number: 10373987Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.Type: GrantFiled: February 21, 2018Date of Patent: August 6, 2019Assignee: Samsung Display Co., Ltd.Inventor: Dae Geun Lee
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Patent number: 10366951Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: June 12, 2017Date of Patent: July 30, 2019Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Patent number: 10366904Abstract: Articles including a glass-based substrate with holes, semiconductor packages including an article with holes, and methods of fabricating holes in a substrate are disclosed. In one embodiment, an article includes a glass-based substrate having a first surface, a second surface, and at least one hole extending from the first surface. The at least one hole has an interior wall having a surface roughness Ra that is less than or equal to 1 ?m. The at least one hole has a first opening having a first diameter that is present the first surface. A first plane is defined by the first surface of the glass-based substrate based on an average thickness of the glass-based substrate. A ratio of a depression depth to the first diameter of the at least one hole is less than or equal to 0.007.Type: GrantFiled: September 6, 2017Date of Patent: July 30, 2019Assignee: Corning IncorporatedInventors: Andres Covarrubias Jaramillo, Yuhui Jin, Frank Andrew Kramer, IV, Ekaterina Aleksandrovna Kuksenkova, Daniel Wayne Levesque, Jr., Garrett Andrew Piech, Aric Bruce Shorey, Robert Stephen Wagner
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Patent number: 10367092Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.Type: GrantFiled: January 3, 2017Date of Patent: July 30, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Setsuko Wakimoto, Masanobu Iwaya
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Patent number: 10354940Abstract: According to the present invention, a semiconductor device includes a first metal plate, a second metal plate provided above the first metal plate, a third metal plate provided above the second metal plate, a first semiconductor chip provided between the first metal plate and the second metal plate, a second semiconductor chip provided between the second metal plate and the third metal plate and a cooling member, wherein the first metal plate has a first cooling portion that is in contact with the cooling member, the second metal plate has a second cooling portion that is in contact with the cooling member, and the third metal plate has a third cooling portion that is in contact with the cooling member.Type: GrantFiled: February 19, 2018Date of Patent: July 16, 2019Assignee: Mitsubishi Electric CorporationInventors: Tetsujiro Tsunoda, Toru Ichimura
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Patent number: 10340155Abstract: A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.Type: GrantFiled: April 14, 2016Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, Tien-Chung Yang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 10332942Abstract: An OLED touch display device includes a first electrode layer, a second electrode layer facing the first electrode layer, a light-emitting layer between the first electrode layer and the second electrode, and a third electrode layer on a side of the first electrode layer. The first electrode layer functions as a cathode of the light-emitting layer, and the second electrode layer functions as an anode of the light-emitting layer. The first electrode layer and the third electrode layer cooperatively form a capacitive force sensing element. The first electrode layer also functions as touch sensing electrode.Type: GrantFiled: July 21, 2017Date of Patent: June 25, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu
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Patent number: 10332830Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.Type: GrantFiled: May 11, 2017Date of Patent: June 25, 2019Assignee: MEDIATEK INC.Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
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Patent number: 10325829Abstract: A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body.Type: GrantFiled: October 24, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerard McVicker, Sri M. Sri-Jayantha
