Patents Examined by Hoa B. Trinh
  • Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method
    Patent number: 10515939
    Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 24, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yi-Hung Chen, Yuan-Chin Liu
  • Thermoelectric cooler (TEC) for spot cooling of 2.5D/3D IC packages
    Patent number: 10504816
    Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: December 10, 2019
    Assignee: Google LLC
    Inventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
  • Transistor array panel
    Patent number: 10497812
    Abstract: A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUMG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Gwang Min Cha, Dong Min Lee
  • Integrated circuit device and method of manufacturing the same
    Patent number: 10497649
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Semiconductor devices and methods of making the same
    Patent number: 10490488
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Roger M. Arbuthnot, Stephen St. Germain
  • Power semiconductor device
    Patent number: 10483175
    Abstract: An object of the present invention to provide a technique which can put flexibility into positions, positional relationships, and sizes of constituent elements. A power semiconductor device includes: a substrate on which a semiconductor chip is disposed; an electrode which has one end fixed to the substrate and stands upright on the substrate; and an insulating case which houses the electrode and has a part opposed to the other end of the electrode. The power semiconductor device includes a conductive nut which is inserted into the case in the part of the case and a conductive component which electrically connects the other end of the electrode and the nut.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shoko Araki, Yukimasa Hayashida, Ryutaro Date
  • Semiconductor device and method for manufacturing the same
    Patent number: 10483115
    Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Heat management system
    Patent number: 10468331
    Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface. The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Je-young Chang, Jae W. Kim, Ravindranath V. Mahajan, Blake Rogers, Devdatta Kulkarni
  • Semiconductor device and method of manufacturing same
    Patent number: 10454059
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Stacked semiconductor dies including inductors and associated methods
    Patent number: 10446527
    Abstract: Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Semiconductor device
    Patent number: 10446460
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
  • Routing for three-dimensional integrated structures
    Patent number: 10446535
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 15, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Semiconductor devices
    Patent number: 10446774
    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yi-Koan Hong, Kwang-Jin Moon, Nae-In Lee, Ho-Jin Lee
  • Arc-resistant crackstop
    Patent number: 10438902
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vincent J. McGahay, Nicholas A. Polomoff, Shaoning Yao, Anupam Arora
  • Display apparatus
    Patent number: 10439017
    Abstract: A display apparatus includes a substrate having a first area, a second area, and a bending area disposed therebetween. The substrate is bent at the bending area about a bending axis. An inorganic insulating layer is disposed over the substrate and includes an opening or groove corresponding to the bending area. An organic material layer fills the opening or groove. A first conductive layer extends from the first area to the second area through the bending area. The first conductive layer is disposed over the organic material layer and includes a multipath portion having a plurality of through holes. A length of the multipath portion, in a direction from the first area to the second area, is greater than a width of the opening or groove, in the direction from the first area to the second area.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dongsoo Kim, Wonkyu Kwak, Kwangmin Kim, Kiwook Kim, Joongsoo Moon, Hyunae Park, Jieun Lee, Changkyu Jin
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 10431516
    Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 1, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Semiconductor package
    Patent number: 10431547
    Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geol Nam, Young Lyong Kim
  • Electronic device package
    Patent number: 10424571
    Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Choi, Eun-Seok Song, Seung-Yong Cha, Yun-Hee Lee
  • Dual airgap structure
    Patent number: 10395980
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Motoi Ichihashi, Atsushi Ogino
  • Array substrate and method of mounting integrated circuit using the same
    Patent number: 10373987
    Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee