Patents Examined by Hoa B. Trinh
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Patent number: 10622458Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.Type: GrantFiled: May 19, 2017Date of Patent: April 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
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Patent number: 10615747Abstract: A vibrator device has a base that has a first terminal, a circuit element that is disposed on the base and has a second terminal, a vibrator that includes a vibrator element and a vibrator element package, and is positioned between the first terminal and the second terminal in plan view of the base, a wiring unit that is disposed on the vibrator, a first wire that electrically connects the first terminal and the wiring unit together, and a second wire that electrically connects the wiring unit and the second terminal together.Type: GrantFiled: March 7, 2018Date of Patent: April 7, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Hisahiro Ito, Tetsuya Otsuki, Mitsuaki Sawada
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Patent number: 10615048Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate including a device region, and forming a functional layer on the substrate. The method also includes forming a plurality of discrete initial core layers on the functional layer. Adjacent initial core layers are spaced apart by a first gap. In addition, the method includes forming a sidewall spacer on a sidewall surface of an initial core layer, and forming a first opening in the functional layer by removing the functional layer at a bottom of the first gap. Moreover, the method includes forming a core layer and a second gap between sidewall spacers by performing a patterning process to remove a portion of the initial core layer. Further, the method includes forming a second opening by removing the functional layer exposed at a bottom of the second gap.Type: GrantFiled: August 30, 2018Date of Patent: April 7, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Duohui Bei
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Patent number: 10600737Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.Type: GrantFiled: October 2, 2017Date of Patent: March 24, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
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Patent number: 10593641Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.Type: GrantFiled: May 20, 2016Date of Patent: March 17, 2020Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yuedong Qiu, Chengchung Lin
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Patent number: 10573791Abstract: Quantum dot polymer composites for on-chip light emitting diode applications are described. In an example, a composite for on-chip light emitting diode application includes a polymer matrix, a plurality of quantum dots dispersed in the polymer matrix, and a base dispersed in the polymer matrix.Type: GrantFiled: September 19, 2017Date of Patent: February 25, 2020Assignee: OSRAM Opto Semiconductors GmbHInventors: Kari N. Haley, Benjamin Daniel Mangum, Weiwen Zhao, Nathan Evan Stott, Juanita N. Kurtin
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Patent number: 10573633Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.Type: GrantFiled: December 4, 2017Date of Patent: February 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Sun Kim, Hyun Jae Kang, Tae Hoi Park, Jin Seong Lee, Eun Sol Choi, Min Keun Kwak, Byung Kap Kim, Sung Won Choi
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Patent number: 10553544Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: October 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10553569Abstract: A device includes a semiconductor structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side contact metal, a molding compound layer and a backside contact metal, and wherein the front side contact metal is between the plurality of bottom package bumps and the molding compound layer and a metal shielding layer on a top surface, sidewalls of the semiconductor structure and portions of a bottom surface of the bottom package, wherein the metal shielding layer is in direct contact with an edge of at least one of the front side contact metal and the backside contact metal.Type: GrantFiled: September 8, 2017Date of Patent: February 4, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Po-Hao Tsai, Jing-Cheng Lin, Li-Hui Cheng
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Patent number: 10529689Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.Type: GrantFiled: July 26, 2017Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventor: Shing-Yih Shih
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Patent number: 10515873Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: GrantFiled: September 7, 2017Date of Patent: December 24, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
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Patent number: 10515939Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.Type: GrantFiled: February 3, 2016Date of Patent: December 24, 2019Assignee: MEDIATEK INC.Inventors: Yi-Hung Chen, Yuan-Chin Liu
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Patent number: 10504816Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.Type: GrantFiled: September 6, 2017Date of Patent: December 10, 2019Assignee: Google LLCInventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
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Patent number: 10497812Abstract: A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.Type: GrantFiled: February 17, 2017Date of Patent: December 3, 2019Assignee: SAMSUMG DISPLAY CO., LTD.Inventors: Dong Hee Lee, Gwang Min Cha, Dong Min Lee
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Patent number: 10497649Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
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Patent number: 10490488Abstract: In one embodiment, methods for making semiconductor devices are disclosed.Type: GrantFiled: January 15, 2018Date of Patent: November 26, 2019Assignee: Semiconductor Components Industries, LLCInventors: Roger M. Arbuthnot, Stephen St. Germain
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Patent number: 10483175Abstract: An object of the present invention to provide a technique which can put flexibility into positions, positional relationships, and sizes of constituent elements. A power semiconductor device includes: a substrate on which a semiconductor chip is disposed; an electrode which has one end fixed to the substrate and stands upright on the substrate; and an insulating case which houses the electrode and has a part opposed to the other end of the electrode. The power semiconductor device includes a conductive nut which is inserted into the case in the part of the case and a conductive component which electrically connects the other end of the electrode and the nut.Type: GrantFiled: December 4, 2015Date of Patent: November 19, 2019Assignee: Mitsubishi Electric CorporationInventors: Shoko Araki, Yukimasa Hayashida, Ryutaro Date
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Patent number: 10483115Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.Type: GrantFiled: August 31, 2017Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Hua Chou, Kuo-Sheng Chuang
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Patent number: 10468331Abstract: A heat management system may include a die package. The die package may include a housing. The housing may include a housing surface. The housing may include a housing inlet port. The housing inlet port may be in communication with the housing surface. The housing may include a housing outlet port. The housing outlet port may be in communication with the housing surface. The heat management system may include a manifold. The manifold may be configured to couple with the housing. The manifold may include a manifold surface. The manifold surface may be configured to mate with the housing surface. The manifold may include a manifold inlet port. The manifold inlet port may be in communication with the manifold surface. The manifold may include a manifold outlet port. The manifold outlet port may be in communication with the manifold surface.Type: GrantFiled: January 12, 2018Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Je-young Chang, Jae W. Kim, Ravindranath V. Mahajan, Blake Rogers, Devdatta Kulkarni
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Patent number: 10454059Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.Type: GrantFiled: November 28, 2017Date of Patent: October 22, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
