Patents Examined by Hoa B. Trinh
  • Semiconductor device fabricating method
    Patent number: 8999814
    Abstract: A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: April 7, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Takashi Shiigi
  • Semiconductor device and method for making same
    Patent number: 8994179
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • System for clamping heat sink
    Patent number: 8994166
    Abstract: A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: March 31, 2015
    Assignee: Harman International Industries, Incorporated
    Inventor: Greg Mlotkowski
  • Circuit board, semiconductor element, semiconductor device, method for manufacturing circuit board, method for manufacturing semiconductor element, and method for manufacturing semiconductor device
    Patent number: 8987899
    Abstract: A circuit board includes: an electrode portion which has a copper layer, a copper oxide layer formed thereon, and a removal portion formed by partially removing the copper oxide layer so as to partially expose the copper layer from the copper oxide layer; and a solder bump for flip chip mounting formed on the copper layer exposed by the removal portion.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: March 24, 2015
    Assignee: Sony Corporation
    Inventor: Hiroshi Asami
  • Headphone device
    Patent number: 8983110
    Abstract: A headphone device including a driver unit, and an ear-hook hanger of a loop shape that is integrated with the driver unit and supports an entire circumference of an ear capsule is provided.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Keitaro Fujiwara, Katsunori Murozaki
  • Lead frame based semiconductor device with routing substrate
    Patent number: 8980690
    Abstract: A semiconductor device including a lead frame, a routing substrate disposed within the lead frame, and an active component mounted on the routing substrate. The active component has a plurality of die pads. The routing substrate includes a set of first bond pads, a set of second bond pads, and interconnections, where each interconnection provides an electrical connection between a first bond pad and a corresponding second bond pad. The semiconductor device further includes electrical couplings between one or more of die pads of the active component and corresponding first bond pads of the routing substrate, as well as electrical couplings between leads of the lead frame and respective second bond pads of the routing substrate.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Penglin Mei, You Ge, Meng Kong Lye
  • Wafer level package, chip size package device and method of manufacturing wafer level package
    Patent number: 8975736
    Abstract: A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 10, 2015
    Assignee: OMRON Corporation
    Inventors: Toshiaki Okuno, Katsuyuki Inoue, Takeshi Fujiwara, Tomonori Seki
  • Co-axial restraint for connectors within flip-chip packages
    Patent number: 8970041
    Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons
  • Semiconductor device and method of manufacturing semiconductor device
    Patent number: 8962440
    Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 24, 2015
    Assignee: Sony Corporation
    Inventor: Satoru Wakiyama
  • Semiconductor device and method of manufacturing the same
    Patent number: 8962394
    Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takumi Ihara
  • TSV structures and methods for forming the same
    Patent number: 8956966
    Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Wen-Chih Chiou, Ku-Feng Yang, Tsang-Jiuh Wu, Jing-Cheng Lin
  • Semiconductor device and production method thereof
    Patent number: 8951905
    Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Kazuhiko Itaya
  • Semiconductor device
    Patent number: 8952505
    Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiju Yamada, Masaaki Ishida
  • Actinic-ray- or radiation-sensitive resin composition, actinic-ray- or radiation-sensitive film therefrom and method of forming pattern using the composition
    Patent number: 8951890
    Abstract: Provided is an actinic-ray- or radiation-sensitive resin composition including (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, (B) an onium salt containing a nitrogen atom in its cation moiety, which onium salt when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, and (C) a compound that when exposed to actinic rays or radiation, generates an acid, the compound being any of compounds of general formulae (1-1) and (1-2) below.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 10, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Kei Yamamoto, Mitsuhiro Fujita, Tomoki Matsuda
  • Apparatus and method for increasing bandwidths of stacked dies
    Patent number: 8952548
    Abstract: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-An Chi, Mark Shane Peng
  • Signal shifting to allow independent control of identical stacked memory modules
    Patent number: 8952515
    Abstract: Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and third modules, each of the first, second and third modules having a plurality of stacked memory dice, at least some of the plurality of stacked memory dice including a Chip Enable (CE) signal electrically accessible from a bottom surface of a corresponding module of the first, second and third modules. The apparatus may comprise a Package-on-Package (PoP) structure where the first, second and third modules are attached to one another such that an individual access to each CE signal associated with the PoP structure is provided from the bottom surface of the corresponding module.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Robert Naylor Schenck, Steven Eskildsen
  • Extended liner for localized thick copper interconnect
    Patent number: 8946896
    Abstract: A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: February 3, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: David Moreau, Jerome Ciavatti
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 8928156
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Electromigration resistant via-to-line interconnect
    Patent number: 8922022
    Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Paul S. McLaughlin, Timothy D. Sullivan
  • Copper bump structures having sidewall protection layers
    Patent number: 8922004
    Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ya-Hsi Hwung, Hsin-Yu Chen, Po-Hao Tsai, Yan-Fu Lin, Cheng-Lin Huang, Fang Wen Tsai, Wen-Chih Chiou