Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract: Multi-chip quad flat no-lead (QFN) packages and methods for making the same are disclosed. A multi-chip package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die mounted on the first die and including a plurality of second bond pads, wherein selected second bond pads are wire-bonded to a second side, opposite the first side, of the leadframe. Another package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die flip-chip mounted on a second side of the leadframe and including a plurality of second bond pads, wherein selected second bond pads are bonded to the second side of the leadframe. Other embodiments are also described.

Abstract: An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.

Abstract: In a method for producing a radiation-emitting optoelectronic component, a semiconductor chip is mounted by a first main area onto a carrier body and is electrically conductively connected at a first contact area to a first connection region, and a transparent electrically insulating encapsulation layer is applied to the chip and the carrier body. A first cutout in the encapsulation layer for at least partly uncovering a second contact area of the chip is produced, and a second cutout in the encapsulation layer for at least partly uncovering a second connection region of the carrier body is produced. Finally, an electrically conductive layer, which electrically conductively connects the second contact area of the semiconductor chip and the second connection region of the carrier body, is applied.

Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract: A power module configured to arrange a first electrode on a surface of which a first switching device is bonded, a second electrode on a surface of which a second switching device is bonded, and a third electrode by stacking the first electrode, the first switching device, the second electrode, the second switching device, and the third electrode in this order from the bottom in a stacking direction, characterized by first through third electrode pieces each connected to the first through third electrodes, first and second signal lines each connected to the first and second switching devices, wherein the first through third electrode pieces and the first and second signal lines are provided extending outward in the same plane as the second electrode.

Abstract: Between a logic LSI (4) arranged on one side of a DRAM (1) and jointed to the DRAM and a radiating member (6) arranged on the other side of the DRAM (1) for irradiating the heats of the DRAM (1) and the logic LSI (4), there is disposed a heat bypass passage (5), which extends inbetween while bypassing the DRAM (1). Thus, it is possible to provide a semiconductor device, which can irradiate the heat generated from the logic LSI such as CPU or GPU thereby to reduce the temperature rise and the temperature distribution.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.

Abstract: Methods for fabricating light emitting diode (LED) chips one of which comprises flip-chip mounting a plurality of LEDs on a surface of a submount wafer and forming a coating over said LEDs. The coating comprising a conversion material at least partially covering the LEDs. The coating is planarized to the desired thickness with the coating being continuous and unobstructed on the top surface of the LEDs. The LEDs chips are then singulated from the submount wafer. An LED chip comprising a lateral geometry LED having first and second contacts, with the LED flip-chip mounted to a submount by a conductive bonding material. A phosphor loaded binder coats and at least partially covers the LED. The binder provides a substantially continuous and unobstructed coating over the LED. The phosphor within the coating absorbs and converts the wavelength of at least some of the LED light with the coating planarized to achieve the desired emission color point of the LED chip.

Abstract: The present invention provides a wafer (3) comprising a through-wafer via (7) through the wafer (3) formed by a through-wafer via hole (9) and at least a first conductive coating (25). A substantially vertical sidewall (11) of the through-wafer via hole (9) except for a constriction (23) provides a reliable through-wafer via (7) occupying a small area on the wafer. The wafer (3) is preferably made of a semiconductor material, such as silicon, or a glass ceramic. A method for manufacturing such a wafer (3) is described.

Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.

Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Abstract: A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Abstract: One aspect of the present invention is a three-dimensional integrated circuit 1 including a first semiconductor chip and a second semiconductor chip that are layered on each other, wherein each of (i) a wiring layer closest to an interface between the first and second semiconductor chips among wiring layers of the first semiconductor chip and (ii) a wiring layer closest to the interface among wiring layers of the second semiconductor chip includes a power conductor area and a ground conductor area, a layout of the power conductor area and the ground conductor area in the first semiconductor chip is the same as a layout of the power conductor area and the ground conductor area in the second semiconductor chip, and the power conductor area in the first semiconductor chip at least partially faces the ground conductor area in the second semiconductor chip with an insulation layer therebetween.

Abstract: A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.

Abstract: A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.