Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the plurality of corner band stacks is oriented at about a predetermined angle and extends from a first sawing trace to a second sawing trace. In a specific embodiment, if a structural fault in the at least one corner area occurs, the structural fault is predisposed to extend at about the predetermined angle.

Abstract: An image sensor includes a first photodiode formed in a semiconductor substrate at a depth reachable by red light, a second photodiode disposed on or over the first photodiode in the semiconductor substrate at a depth reachable by blue light, a third photodiode disposed adjacent to the second photodiode, a plug connected to the first photodiode, transistor structures on the semiconductor substrate and electrically connected with the first, second and third diodes, an insulating layer covering the transistor structures, and microlenses on the insulating layer.

Abstract: A semiconductor device, includes: a wiring substrate having a wiring pattern on a front surface thereof; a first semiconductor chip mounted on the front surface of the wiring substrate; a first heat radiator having a first recess housing the first semiconductor chip and making contact with the front surface of the wiring substrate and the first semiconductor chip directly or with a first insulation layer; a second heat radiator making contact with a rear surface of the wiring substrate directly or with a second insulation layer; and a first fixing member passing through the first heat radiator, the wiring substrate, and the second heat radiator, and pressing the first heat radiator and the second heat radiator to the wiring substrate.

Abstract: An image display medium includes: a first substrate; a second substrate facing the first substrate; a first bonding layer provided inside at least one of the first substrate and the second substrate; and an insulating layer fixed to the at least one of the first substrate and the second substrate by the first bonding layer, wherein the first bonding layer has a Young's modulus smaller than the substrate formed with the insulating layer and the insulating layer.

Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract: When connecting a semiconductor device such as an IC chip with a circuit board by the flip-chip method, a semiconductor device is provided without forming bumps thereon, which enables highly reliable and low cost connection between the IC chip and circuit board while ensuring suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board. The bumpless semiconductor device is provided with electrode pads 2 on the surface thereof and with a passivation film 3 at the periphery of the electrode pads 2, and conductive particles 4 are metallically bonded to the electric pads 2. Composite particles in which a metallic plating layer is formed at the surface of resin particles are employed as the conductive particles 4.

Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.

Abstract: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.

Abstract: A via hole having a fine hole land includes a first conductive layer formed on an inner wall of the via hole, the first conductive layer being in contact with a hole formed in an insulation layer and extendedly projected to the outside and having the same diameter as the hole in the insulation layer; a second conductive layer contacted with the first conductive layer and formed on an inner wall thereof and projected to the outside and having the same height as the first conductive layer; and a circuit line, formed on the insulation layer, to connect the first conductive layer extendedly projected to the outside of hole in the insulation layer, where the second conductive layer has the same height as the first conductive layer and the fine hole land is connected to wire bonding pad or solder ball pad through the circuit line.

Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.

Abstract: Disclosed is that in a method of manufacturing a semiconductor device of the present invention, when first and second P type diffusion layers using as a backgate region, these layers are formed in such a way that their impurity concentration peaks are shifted, respectively. Then, in the backgate region, a concentration profile of a region where an N type diffusion layer is formed is gradually established. After that, impurity ions, which form the N type diffusion layer, are implanted, and thereafter a thermal treatment is performed to diffuse the N type diffusion layer in a y shape at a lower portion of a gate electrode. This manufacturing method makes it possible to implement an electric filed relaxation in a drain region.

Abstract: Disclosed are an isolation structure and a method for forming the same. The present isolation structure includes a substrate having a first semiconductor layer having a first lattice parameter, a second semiconductor layer having a second lattice parameter larger than the first lattice parameter, and a strained semiconductor layer; a well in the substrate; a plurality of isolation layers in the strained semiconductor layer and the second semiconductor layer, defining an active region; and a plurality of punch stop layers under the isolation layers.

Abstract: The present invention relates to a nickel alloy sputtering target comprising 1 to 30 at % of Cu; 2 to 25 at % of at least one element selected from among V, Cr, Al, Si, Ti and Mo; remnant Ni and unavoidable impurities so as to inhibit the Sn diffusion between a solder bump and a substrate layer or a pad. Provided are a nickel alloy sputtering target and a nickel alloy thin film for forming a barrier layer having excellent wettability with the Pb-free Sn solder or Sn—Pb solder bump, and capable of inhibiting the diffusion of Sn being a soldering component and effectively preventing the reaction with the substrate layer upon forming a Pb-free Sn solder or Sn—Pb solder bump on a substrate such as a semiconductor wafer or electronic circuit or a substrate layer or pad of the wiring or electrode formed thereon.

Abstract: Ferroelectric capacitors are provided that include an integrated circuit substrate and a supporting insulation layer on the integrated circuit substrate having a face and a trench in the face. An oxidation barrier conductive layer is provided in the trench and a lower electrode is provided on the oxidation barrier conductive layer. A ferroelectric layer is provided on the lower electrode and an upper electrode is provided on the ferroelectric layer. Related methods of fabricating ferroelectric capacitors are also provided.

Abstract: A semiconductor device including a semiconductor substrate containing a plurality of electrode pads and a passivation film with an opening that exposes a central area of each of the electrode pads, and a bump electrically connected to each of the electrode pads, the bump being disposed to overlap the opening and an end of the opening, wherein at least part of an area contacting the bump on a surface of the passivation film is an uneven surface.

Abstract: A charge coupled device comprises a semiconductor substrate of one conductive type, a first charge couple device having a series of electrodes linearly arranged on the semiconductor substrate, a second charge coupled device diverged into tow lines at an end of the first charge coupled device, detectors, each of which detects a signal transferred by one of two lines of the diverged second charge coupled device, and output devices, each of which outputs the signal detected by one of the detectors, wherein a plane shape of a last electrode of the first charge coupled device connecting to the diverged second charge coupled device is a shape wherein a length of a transfer channel of the last electrode becomes shorter as going far from a right angled direction of a transfer direction of the first charge coupled device starting from a boundary part of divergence of the diverged second charge coupled device.

Abstract: Methods for assembling a die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. The method includes coupling a first surface of a substrate to a first surface of a heat spreader, mounting a first surface of an IC die to the first surface of the heat spreader within a central cavity of the substrate, coupling a plurality of bond pads on a second surface of the IC die to corresponding bond pads on a second surface of the substrate with a plurality of wire bonds, and coupling a first surface of an interposer to the second surface of said IC die. A central opening is open at the first surface of the substrate and the second surface of the substrate. The central opening overlaps the central cavity formed in the first surface of the heat spreader. A plurality of electrically conductive bumps on the second surface of the IC die are coupled to corresponding bond pads on the first surface of said interposer.